Micron Technology Incorporated

Aptina Imaging Corporation

Michael W Morrison

Walter L Moden

Corey Jacobsen

Derek J Gochnour

Carol M Morrison

Snap-on accessory holder for golf bag

Semiconductor device packages formed in accordance with methods of packaging semiconductor dice in grid array-type semiconductor device packages using conventional lead frame or lead lock tape assembly equipment are disclosed. Circuitry-bearing structure having an electrically insulating layer that carries redistribution electrical connections having redistributed bond pads and conductive traces and which is supported from beneath by a support layer are configured for securing to the active surface of a semiconductor die. The support layer may comprise an electrically conductive material, which may act as a heat sink or as a ground plane for the packaged semiconductor device. A semiconductor device and a semiconductor assembly are also provided.

Ball grid array structures having tape-based circuitry

Microelectronic devices having an EMI shield, systems including such microelectronic devices, and methods for manufacturing such microelectronic devices. One embodiment of a microelectronic device comprises an imaging system comprising a microelectronic die, an optics assembly, and an electromagnetic interference (EMI) shield. The microelectronic die includes an image sensor, processing components electrically coupled to the image sensor, a first interconnect electrically isolated from the processing components, and a second interconnect electrically coupled to the processing components. The optics assembly is aligned with the image sensor, and the electromagnetic interference (EMI) shield is between the optics assembly and the processing components. The EMI shield is electrically coupled to the first interconnect.

Microelectronic devices having an EMI shield and associated systems and methods

A semiconductor device assembly and method of making the device are disclosed. The assembly comprises a semiconductor die attached to an electrically conductive layer, which is, in turn, connected to a dielectric layer carrying conductive traces of an electrical connection layer. The conductive traces provide connection between an array of discrete conductive elements and bonding wires connected to bond pads of the die. The conductive layer enhances thermal conduction and structural stiffness for the assembly. In addition, the conductive layer provides a voltage reference plane that may be connected to a power source, a ground source, or an intermediate reference voltage. The conductive layer also includes at least one electrical current isolation slot, which segments the conductive layer to help isolate noise induced in one segment of the conductive layer from the other segments.

Semiconductor BGA package having a segmented voltage plane

A semiconductor device assembly and method of making the device are disclosed. The assembly comprises a semiconductor die attached to an electrically conductive layer, which is, in turn, connected to a dielectric layer carrying conductive traces of the electrical connection layer. The conductive traces provide connection between an array of discrete conductive elements and bonding wires connected to bond pads of the die. The conductive layer enhances thermal conduction and structural stiffness for the assembly. In addition, the conductive layer provides a voltage reference plane that may be connected to a power source, a ground source, or an intermediate reference voltage. The conductive layer also includes at least one electrical current isolation slot, which segments the conductive layer to help isolate noise induced in one segment of the conductive layer from the other segments.

Method of making semiconductor BGA package having a segmented voltage plane

Semiconductor device packages formed in accordance with methods of packaging semiconductor dice in grid array-type semiconductor device packages using conventional lead frame or lead lock tape assembly equipment are disclosed. Circuitry-bearing segments having an electrically insulating layer that carries redistribution circuitry and redistributed bond pads and which is supported from beneath by a support layer are secured to the active surface of a semiconductor die. The support layer may comprise an electrically conductive material, which may act as a heat sink or as a ground plane for the packaged semiconductor device. The methods provide increased accuracy with which segments are placed on a semiconductor die relative to the placement accuracies provided when pick-and-place equipment is used to position conventional grid array substrates relative to semiconductor dice.

Ball grid array structures and tape-based method of manufacturing same

A semiconductor device assembly and method of making the devices are disclosed. The assembly comprises a semiconductor die attached to an electrically conductive layer, which is, in turn, connected to a dielectric layer carrying conductive traces of the electrical connection layer. The conductive traces provide connection between an array of discrete conductive elements and bonding wires connected to bond pads of the die. The conductive layer enhances thermal conduction and structural stiffness for the assembly. In addition, the conductive layer provides a voltage reference plane that may be connected to a power source, a ground source, or an intermediate reference voltage. The conductive layer also includes at least one electrical current isolation slot, which segments the conductive layer to help isolate noise induced in one segment of the conductive layer from the other segments.

Semiconductor BGA package having a segmented voltage plane and method of making

An apparatus and method of removably interconnecting a reduced-sized memory card with an extension member. A locking mechanism may be formed in a peripheral end portion of the reduced-sized memory card that may include an entry surface and a ledge. The extension member may include a biasing portion that slidably engages the entry surface and removably interconnects with the ledge. With this arrangement, the extension member may easily be secured and removed from the reduced-sized memory card, allowing easy interchangeability between a standard-sized socket of one electronic device and a reduced-sized socket of another electronic device.

Reduced-sized memory card package, length-extending adaptor and method of forming adaptor

An apparatus and method of removably interconnecting a reduced-sized memory card with an extension member. The locking mechanism may be formed in a peripheral end portion of the reduced-sized memory card that may include an entry surface and a ledge. The extension member may include a biasing portion that slidably engages the entry surface and removable interconnects with the ledge. With this arrangement, the extension member may easily be secured and removed from the reduced-sized memory card, allowing easy interchangeability between a standard-sized socket of one electronic device and a reduced-sized socket of another electronic device.

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Boise, ID, United States of America

Michael W Morrison