Agere Systems Inc.

Michael W Hathaway

Joel Roger Davidson

Mauricio Calle

James Thomas Kirk

Gregg Alan Bouchard

David Sonnier

Leslie Zsohar

Christopher Brian Walton

A packet processing system comprises first processing circuitry for performing a first function, and first memory circuitry coupled to the first processing circuitry for storing received packets, wherein at least a portion of the packets stored by the first memory circuitry are usable by the first processing circuitry in accordance with the first function. The packet processing system further comprises at least second processing circuitry for performing a second function, and at least second memory circuitry coupled to the second processing circuitry for storing at least a portion of the same packets stored in the first memory circuitry, wherein at least a portion of the packets stored in the second memory circuitry are usable by the second processing circuitry in accordance with the second function. In an illustrative embodiment, the first processing circuitry and the second processing circuitry operate in a packet switching device such as a router. In such case, the first processing circuitry and the second processing circuitry operate between a packet network interface and a switch fabric of the packet switching device.

Methods and apparatus for using multiple reassembly memories for performing multiple functions

A network processor or other type of processor includes a packet analyzer and first memory circuitry operatively coupled to the packet analyzer. The packet analyzer is operative to at least partially analyze one or more packets received by the processor in order to determine for a given one of the packets a portion of the packet to be stored in the first memory circuitry. The portion of the given packet when stored in the first memory circuitry is thereby made accessible for subsequent processing within the processor, without requiring access to second memory circuitry associated with the processor and configured to store substantially the entire given packet. The packet analyzer may be configured to utilize a value stored in a register of the processor to determine the portion of the given packet to be stored in the first memory circuitry. The register may be one of a number of registers which implement a look-up table accessible to the packet analyzer. The look-up table includes multiple entries, each having packet categorizing information, such as port number or packet flow identifier, and an associated number of blocks of the packet to be stored in the first memory circuitry. The value stored in a given one of the registers may be dynamically updatable under control of a host device operatively coupled to the processor.

Processor with reduced memory requirements for high-speed routing and switching of packets

A voice packet processor for use with voice applications employing a fast pattern processor (FPP) and a routing switch processor (RSP) that receive and transmit protocol data units (PDUs) and a method of operation thereof. In one embodiment, the voice packet processor includes (1) a voice packet controller (VPC) configured to receive the PDUs from the FPP and queue the PDUs for processing, (2) a voice packet parser configured to receive the PDUs that are ATM adaptation layer(AAL) cells containing voice data from the VPC, parse the AALcells into at least one Common Part Sublayer (CPS) packet and transmit the at least one CPS packet to the RSP, and (3) a voice packet assembler configured to receive the PDUs that are CPS packets from the VPC, assemble the CPS packets into at least one AALCell and transmit the at least one AALcell to the RSP.

Voice packet processor and method of operation thereof

Growing community of inventors

Austin, TX, United States of America

Michael W Hathaway