International Business Machines Corporation

Michael W Dotson

Howard Thomas Olnowich

James William Feeney

Robert Francis Lusch

Michael Anthony Maniguet

John David Jabusch

Michael Hans Fisher

Charles Jay Alpert

Ruchir Puri

Gi-Joon Nam

Shyam Ramji

Natarajan Viswanathan

Louise Helen Trevillyan

Anthony DeGroff Drumm

Dazhuang J Ma

Matthew D Wise

In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.

Method and apparatus for parallel processing of semiconductor chip designs

A hierarchical method of legalizing the placement of logic cells in the presence of blockages selectively classifies the blockages into at least two different sets based on size (large and small). Movable logic cells are relocated first among coarse regions between large blockages to remove overlaps among the cells and the large blockages without regard to small blockages (while satisfying capacity constraints of the coarse regions), and thereafter the movable logic cells are relocated among fine regions between small blockages to remove all cell overlaps (while satisfying capacity constraints of the fine regions). The coarse and fine regions may be horizontal slices of the placement region having a height corresponding to a single circuit row height of the design. Cells are relocated with minimal perturbation from the previous placement, preserving wirelength and timing optimizations. The legalization technique may utilize more than two levels of granularity with multiple relocation stages.

Legalization of VLSI circuit placement with blockages using hierarchical row slicing

Under the present invention, a proposed placement of I/O pads into one or more groups on a chip analyzed. Specifically, using resources such as a control file, cross-reference table, an I/O limit table, and an optional information file, a group switching current for each proposed I/O pad group is automatically calculated and compared to predetermined maximum switching current(s). If an I/O pad group exhibits a switching current that exceeds its predetermined maximum, corrective action is taken. Such action can include, for example, relocation of an I/O pad from an overloaded I/O pad group to another I/O pad group, insertion of an additional power pad into the overloaded I/O pad group, etc.

System, method and program product for positioning I/O pads on a chip

An apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. The apparatus is relatively easy to implement and inexpensive to build. The communication media is switch-based and is fully parallel, supporting nodes interconnected by the switching network.

Apparatus for coupling a bus-based architecture to a switch network

A method and apparatus for reducing the software overhead of message passing in parallel systems. Special purpose hardware assists in constructing each data message sent through a network. Message passing systems generally require that every message be prefixed with a message header describing the key control parameters of the message. The software task is to construct the message header for every message individually and to transmit the header prefixed to every message. The software is relieved of constructing the message header and uses special purpose hardware to accomplish the job more efficiently.

Automatic hardware message header generator

A conversion apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel (IBM Trademark) bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. A conversion apparatus controls the transfer of data messages from one nodal element across a switch network to another nodal element by using direct memory access capabilities controlled by intelligent bus masters. This approach does not require interactive support from the processor at either nodal element during the message transmission, and frees up both processors to perform other tasks. The communication media is switch-based and is fully parallel, supporting n transmissions simultaneously, where n is the number of nodes interconnected by the switching network.

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Binghamton, NY, United States of America

Michael W Dotson