Advanced Micro Devices Corporation

Fujitsu Corporation

Adesto Technologies Corporation

Other

Spansion Llc.

Michael Van Buskirk

Johnny C Chen

Yasushi Kasa

Nancy S Leong

Tiao-Hua Kuo

Chi K Chang

Narbeh Derhacobian

Daniel Sobek

Sameer S Haddad

Mark W Randolph

Pau-Ling Chen

Darlene G Hamilton

Colin Stewart Bill

Binh Quang Le

Shane Charles Hollmer

Venkatesh P Gopinath

Eugen Gershon

Ming Sang Kwan

John Dinh

Michael S Chung

Derric Lewis

Masaru Yano

John Ross Jameson

Fatima Bathul

Janet S Y Wang

Shoichi Kawamura

Vincent C Leung

Masato Horiike

Narbeth Derhacobian

Daniel Sobeck

Collin Bill

In one embodiment, a capacitive circuit can include: (i) a resistive storage element having a solid electrolyte, a first electrode coupled to a first side of the solid electrolyte, and a second electrode coupled to a second side of the solid electrolyte; (ii) the resistive storage element being configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction to form a conductive path between the first and second electrodes, and being configured to be erased to a high resistance state by application of an erase voltage in a reverse bias direction to substantially dissolve the conductive path; and (iii) a first capacitor having the first electrode coupled to a first side of a first oxide layer, and a third electrode coupled to a second side of the first oxide layer.

Capacitor arrangements using a resistive switching memory cell structure

A resistive switching memory device can include a plurality of resistive memory cells, where each of the resistive memory cells includes: (i) a first diode having an anode coupled to a first word line and a cathode coupled to a common node; (ii) a second diode having an anode coupled to the common node and a cathode coupled to a second word line; and (iii) a resistive storage element having an anode coupled to a bit line and a cathode coupled to the common node, wherein the resistive memory cell is configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction, and to be erased to a high resistance state by application of an erase voltage in a reverse bias direction.

Resistive switching memory device with diode select

The present invention pertains to a technique for determining the level of a bit in a dual sided ONO flash memory cell where each of the bits of the dual sided ONO flash memory cell can be programmed to multiple levels. One or more aspects of the present invention take into consideration the affect that the level of charge on one bit can have on the other bit, otherwise known as complimentary bit disturb. A metric known as transconductance is utilized in making the bit level determination to provide a greater degree of resolution and accuracy. In this manner, determining the bit level in accordance with one or more aspects of the present invention mitigates false or erroneous reads.

Read approach for multi-level virtual ground memory

A bank selector encoder comprises a partition indicator circuit having a plurality of partition boundary indicator terminals, a plurality of inverters arranged in a plurality of columns, with each column of the inverters coupled to a respective one of a plurality of columns of ROM cells in a ROM array and a plurality of bank selector code outputs coupled to respective columns of the inverters. The partition boundary indicator terminals are capable of designating a memory partition boundary to identify an upper memory bank and a lower memory bank. The bank selector encoder is capable of generating an identifying bank selector code for each of a plurality of the predetermined memory partition boundaries. The bank selector encoder outputs code bits of a bank selector code based upon the partition boundary indicator terminals.

Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture

An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using an initial negative gate erase voltage to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. By utilizing a negative gate erase voltage, the cell does not require increased erase time to reduce the cell threshold and avoid incomplete erase conditions as the number of program-erase cycles increases.

Using a negative gate erase to increase the cycling endurance of a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure

An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure having charge stored near both the source and drain. During the erase operation, a negative gate erase voltage is applied along with a positive source and drain voltage to improve the speed of erase operations and performance of the non-volatile memory cell after many program-erase cycles.

Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure

A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option,, a bank selector encoder,coupled to receive a memory partition indicator signal from the memory boundary option,, and a bank selector decoder,coupled to receive a bank selector code from the bank selector encoder,. The decoder,, upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.

A method of erasing a memory cell that has a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains an initial amount of charge. The method includes applying a first voltage across the gate and the first region so that a first portion of the initial amount of charge is removed from the charge trapping region. Next, a second voltage is applied across the gate and the first region so that a second portion of the initial amount of charge is removed from the charge trapping region, wherein the second voltage is different than the first voltage.

Method of erasing non-volatile memory cells

A method for sensing the state of erasure of a flash (EEPROM) memory device. In one embodiment, the source voltage during erase is monitored and compared to a value determined during a characterization procedure. In a second embodiment, the rate of change of the source voltage during erase is determined and compared to a value determined during a characterization procedure. The characterization procedure correlates state of erasure with source voltages and slopes of the rate of change of source voltage versus time curve for the memory cells. The determination of the source voltage and the determination of the rate of change of the source voltage and the associated state of erasure allows modification of the erase procedure.

Concurrent erase verify scheme for flash memory applications

A method of forming flexibly partitioned metal line segments 10 and 12 for separate memory banks in a simultaneous operation flash memory device with a flexible bank partition architecture comprises the steps of providing a basic metal layer 2 comprising a plurality of basic metal layer segments 2a, 2b, 2c, . . . 2j separated by a plurality of gaps 6a, 6b, 6c, . . . 6i, each of the gaps having a predefined gap interval length, and providing a metal option layer 8 comprising a plurality of metal option layer segments on the basic metal layer 2, the metal option layer segments overlapping the gaps between the basic metal layer segments but leaving one of the gaps open, to form the metal line segments for the separate memory banks.

Method of making flexibly partitioned metal line segments for a

A decoding circuit 54 for a simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises an X-decoder 44, a lower bank decoder 58, an upper bank decoder 56, and a plurality of flexibly partitioned conductive lines coupled between the upper and lower bank decoders 56 and 58. The flexibly partitioned conductive lines 60, 62, 64, . . . 74 provide a plurality of bank address pre-decoding bits for the X-decoder 44 to row decode the memory cells along the respective word lines in the memory array 20. The memory array 20 includes a plurality of flexibly partitioned bit lines comprising first and second bit line segments to partition the memory array into upper and lower memory banks. The bit line segments in the upper and lower memory banks are coupled to two Y-decoders 32 and 34 which provide column decoding for the memory cells in the upper and lower memory banks.

Memory address decoding circuit for a simultaneous operation flash

A simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises a memory array 20 including a plurality of memory cells arranged in a plurality of columns and rows, a plurality of bit lines 28 and 30 each coupled to a respective column of the memory cells, each of the bit lines comprising first and second bit line segments separated by a gap designating a memory partition boundary between upper and lower memory banks, and an X-decoder 22 coupled to the respective rows of the memory cells to row decode the memory array in response to receiving upper and lower bank memory addresses. Two pre-decoders 24 and 26 are coupled to the X-decoder 22. Two Y-decoders 32 and 34 are coupled to the bit line segments to provide column decoding for the memory cells in the upper and lower memory banks, respectively.

Simultaneous operation flash memory device with a flexible bank

In the programming of a non-volatile memory device, such as a NAND flash memory device 100, a positive bias voltage V.sub.bias is applied to a bit line 44 to set a respective memory gate 44a in a programmed state. In a further embodiment, the positive bias voltage V.sub.bias is obtained by dividing the select drain gate voltage V.sub.cc using two resistors 56 and 58 connected in series.

Bit line biasing method to eliminate program disturbance in a

A system and method for providing a flash memory is disclosed. The flash memory includes a plurality of memory cells. Each memory cell includes a source and a gate. The method and system include providing a plurality of word lines and a plurality of select devices. Each word line is coupled with the gate of each memory cell of a portion of the plurality of memory cells. Each word line provides a specific voltage to the portion of the plurality of memory cells during a read of a memory cell of the portion of the plurality of memory cells. The plurality of select devices correspond with the plurality of word lines. Each select device is coupled with the source of each memory cell of the portion of the plurality of memory cells coupled with the corresponding word line. Each select device couples the source of each memory cell of the portion of the plurality of memory cell with a specific potential during the read of the memory cell. The method and system reduce the number of memory cells coupled in parallel with the memory cell during the read.

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Saratoga, CA, United States of America

Michael Van Buskirk