Micron Technology Incorporated

Michael V Ho

Scott Eugene Smith

Ravi Kiran Kandikonda

Tyler J Gomm

Byung Sick Moon

Myung Ho Bae

Vijayakrishna J Vankayala

Eric J Smith

Younghoon Oh

An apparatus includes a memory device interface comprising a first data output, a second data output, a third data output, and a fourth data output, as well as a first path corresponding to the first data output, a second path corresponding to the second data output, a third path corresponding to the third data output, and a fourth path corresponding to the fourth data output. The apparatus also includes a signal transmission circuit comprising a first output that when in operation transmits a first clock signal to the first path, the second path, the third path, and the fourth path and a second output that when in operation transmits a second clock signal to the first path, the second path, the third path, and the fourth path.

Delay-locked loop clock sharing

Semiconductor devices having busing layouts configured to reduce on-die capacitance are disclosed herein. In one embodiment, a semiconductor device includes an electrostatic discharge device electrically connected in parallel with an integrated circuit and configured to divert high voltages generated during an electrostatic discharge event away from the integrated circuit. The semiconductor device further includes a signal bus and a power bus electrically connected to the electrostatic discharge device. The signal bus includes a plurality of first fingers grouped into first groups and the power bus includes a plurality of second fingers grouped into second groups. The first groups are positioned generally parallel to and interleaved between the second groups.

Semiconductor devices having electrostatic discharge layouts for reduced capacitance

An exemplary semiconductor device includes a clock generator circuit configured to generate a clock signal, and a duty cycle adjustment circuit configured to receive the clock signal. The duty cycle adjustment circuit includes an adjuster circuit configured to receive a back-bias voltage and to adjust a duty cycle of the clock signal based on the back-bias voltage to provide an output dock signal.

Apparatuses and methods to perform duty cycle adjustment with back-bias voltage

An exemplary semiconductor device includes a clock generator circuit configured to generate a clock signal, and a duty cycle adjustment circuit configured to receive the clock signal. The duty cycle adjustment circuit includes an adjuster circuit configured to receive a back-bias voltage and to adjust a duty cycle of the clock signal based on the back-bias voltage to provide an output clock signal.

A semiconductor device may include a plurality of memory banks and an output buffer that may couple to the plurality of memory banks. The output buffer may produce a data voltage signal representative of data to be read from at least one of the plurality of memory banks to a controller. The semiconductor device may also include a plurality of switches that may couple a voltage source to the output buffer, a first pull-down switch that may drive the output buffer to a low voltage reference level to correct its drive strength. The device also includes a second pull-down switch that may couple the output buffer to the low voltage reference level. The plurality of switches, the first pull-down switch, and the second pull-down switch may each provide the data voltage signal to the output buffer.

Systems and methods for improving output signal quality in memory devices

Memory devices and systems in which array data lines of a local data bus are shared between two or more memory bank groups in a memory array. In one embodiment, a memory device is provided, comprising a memory array, I/O gating circuitry, and a local data bus. The local data bus can include a plurality of array data lines shared between two or more memory bank groups of the memory array. The local data bus can electrically couple and transfer data between the two or more memory bank groups and the I/O gating circuitry. In some embodiments, one or more data latches can be electrically coupled to the local data bus to (i) transfer data off the local data bus to free the plurality of data lines for subsequent data transfers and/or (ii) match varying data propagation timings on the local data with column generations of the memory bank groups.

Memory with a reduced array data bus footprint

A memory device includes a first set of data input/output (I/O) devices configured to communicate a first portion of a data unit to or from an external controller; a second set of data I/O devices configured to communicate a second portion of the data unit to or from the external controller; a data control circuit can share the internal global data lines by multiplexing the timings of the first and second sets of data I/O devices, the data control circuit configured to route the data unit according to a data operation corresponding to the data unit; and a shared data bus coupling both the first set of data I/O devices and the second set of data I/O devices to the data control circuit, the shared data bus configured to relay both the first portion and the second portion of the data unit.

Semiconductor device with a time multiplexing mechanism for size efficiency

A dynamic random-access memory (DRAM) device includes memory banks configured to store data and provide access to the stored data; and a data control circuit coupled to the memory banks, the data control circuit configured to: determine a pointer based on a received command, wherein the pointer corresponds to a target memory bank associated with the received command, and route a set of bits to or from the target memory bank using the pointer. In the long burst length and page mode operations where the array access is targeted in certain Bank Group, the pointer is generated and then allow the groups of data bits flowing through the center freely. This pseudo flow through scheme is low power and fast speed by removing the control of gating commands at each stage of the data path during Read and Write operations.

Semiconductor device with pseudo flow through scheme for power savings

Methods, systems, and devices for mitigating line-to-line capacitive coupling in a memory die are described. A device may include multiple drivers configured to both drive latched data and conduct read and write operations. For example, a memory device may contain two or more memory arrays independently coupled to two drivers via two data lines. One data line may be driven strongly to shield a corresponding memory array from effects associated with data line capacitive coupling. An opposing data line may be driven with data pertaining to an access operation of the memory array to which it is coupled. The opposing data line may be driven concurrently or within a small time difference of the other data line.

Mitigating line-to-line capacitive coupling in a memory die

An electronic device includes a first circuit grouping including a first set of drivers, the first circuit grouping configured to generate a first set of output signals corresponding to a first slew rate; and s second circuit grouping including a second set of drivers, the second circuit grouping configured to generate a second set of output signals corresponding to a second slew rate, wherein the first set of drivers correspond to one or more physical characteristics different than the second set of drivers for introducing different slew rates.

Low power method and system for signal slew rate control

A semiconductor device may include a number of memory banks, an output buffer that couples to the memory banks, a number of switches that couple a voltage source to the output buffer, and a stagger delay circuit. The stagger delay circuit may include a resistor-capacitor (RC) circuit that outputs a current signal that corresponds to a data voltage signal received by the RC circuit. The stagger delay circuit may also include a logic circuit that determines a strength of the current signal and sends a first gate signal to a first portion of the switches based on the strength.

Systems and methods for generating stagger delays in memory devices

A semiconductor device may include a plurality of memory banks and an output buffer that couples to the plurality of memory banks. The output buffer may produce a data voltage signal representative of data to be read from at least one of the plurality of memory banks. The semiconductor device may also include a driver circuit having a pulse generator and a pull-down switch that couples the output buffer to ground, such that the pull-down switch provides the data voltage signal to the output buffer. The semiconductor device may also include a test mode circuit that determines whether the data voltage signal is acceptable and sends an enable signal to the pulse generator in response to the data voltage signal not being acceptable. The enable signal causes the pulse generator to effectively operate with variations in processing, temperature, and voltage properties associated with testing.

Systems and methods for conserving power in signal quality operations for memory devices

Devices, systems, and methods for reducing noise couplings between propagation lines for size efficiency. In one embodiment, a memory device is provided, comprising a memory array and an input/output (I/O) circuit. The I/O circuit can include a first plurality of global data lines and a second plurality of global data lines. The second plurality of global data lines are directly interleaved between the first plurality of global date lines and are configured to shield the first plurality of global data lines. In some embodiments, the first plurality of global data lines are shorter in length than the second plurality of global data lines and are switched before the second plurality of global data lines are switched.

Systems and methods for reducing coupling noise between propagation lines for die size efficiency

A memory device includes a timing circuit configured to: receive an input signal, wherein the input signal is one signal within a group of input signals (e.g., multiple bits or nibbles) that are communicated according to a sequence with each of the input signals individually in serial to parallel operations, and generate a grouped latching timing signal based on the received input signal, wherein the timing signal corresponds to nibbles of the data.

Growing community of inventors

Allen, TX, United States of America

Michael V Ho