Intel Corporation

Michael Tulanowski

Krishnakanth Venkata Sistla

Andrew J Herdrich

Ankush Varma

Vivek Garg

Dean A Mulla

Nikhil Gupta

Nazar Syed Haider

Ripan Das

Adwait Purandare

Yogesh Bansal

Suresh Chemudupati

Aman Sewani

Eric Dehaemer

Nilanjan Palit

Rupal Parikh

Ujjwal Gupta

Pavithra Sampath

Nikethan Shivanand Baligar

Stanley Chen

Stephen Wang

Dorit Shapira

Shruthi Venugopal

Phani Kumar Kandula

Timothy Yee-Kwong Kam

Stephen Paul Haake

Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Hierarchical power management apparatus and method

Growing community of inventors

Fort Collins, CO, United States of America

Michael Tulanowski