Infineon Technologies Austria Ag

Infineon Technologies Ag

Infineon Technologies Dresden Gmbh

Michael Treu

Roland Rupp

Hans Weber

Armin Willmeroth

Thomas Gutt

Ralf Otremba

Rudolf Elpelt

Gabor Mezoesi

Franz Hirler

Ralf Siemieniec

Klaus Schiess

Johannes Baumgartl

Stefan Woehlert

Andreas Moser

Gerald Deboy

Rolf Weis

Michael Rueb

Peter Friedrichs

Uwe Kirchner

Larissa Wehrhahn-Kilian

Andreas Schloegl

Marco Seibt

Wolfgang Peinhopf

Oliver Haeberlen

Dethard Peters

Walter Rieger

Armin Tilke

Heinz Mitlehner

Martin Henning Vielemeyer

Christian Fachmann

Roman Knoefler

Manfred Pippan

Martin Pölzl

Gerhard Nöbauer

Mario Feldvoss

Wolfgang Bartsch

Franz Auerbach

Michael Rüb

Gabriel Konrad Dehlinger

Thomas Rupp

Mario Veldvoss

Kathrin Rueschenschmidt

A semiconductor includes a carrier; a semiconductor element arranged on the carrier; a first row of terminals arranged along a first side face of the carrier; a second row of terminals arranged along a second side face of the carrier opposite the first side face; and an encapsulation body encapsulating the semiconductor element, wherein the semiconductor element comprises a first transistor structure and a second transistor structure, wherein the first row of terminals comprises a first gate terminal, a first sensing terminal coupled, and a first power terminal, wherein the second row of terminals, a second sensing terminal, and a second power terminal.

Semiconductor device including a bidirectional switch

A semiconductor device forming a bidirectional switch includes first and second carriers, first and second semiconductor chips arranged on the first and second carriers, respectively, a first row of terminals arranged along a first side face of the carrier, a second row of terminals arranged along a second side face of the carrier opposite the first side face, and an encapsulation body encapsulating the first and second semiconductor chips. Each row of terminals includes a gate terminal, a sensing terminal and at least one power terminal of the bidirectional switch.

In an embodiment, a method of fabricating a superjunction semiconductor device includes implanting first ions into a first region of a first epitaxial layer using a first implanting apparatus and nominal implant conditions to produce a first region in the first epitaxial layer comprising the first ions and a first implant characteristic and implanting second ions into a second region of the first epitaxial layer, the second region being laterally spaced apart from the first region, using second nominal implanting conditions estimated to produce a second region in the first epitaxial layer having the second ions and a second implant characteristic that lies within an acceptable maximum difference of the first implant characteristic.

Method of manufacturing a superjunction semiconductor device

A semiconductor device forming a bidirectional switch includes a carrier, first and second semiconductor elements arranged on the carrier, a first row of terminals arranged along a first side face of the carrier, a second row of terminals arranged along a second side face of the carrier opposite the first side face, and an encapsulation body encapsulating the first and second semiconductor elements. Each row of terminals includes a gate terminal, a sensing terminal and at least one power terminal of the bidirectional switch.

A semiconductor wafer includes an alignment mark contained within in a kerf region of the semiconductor wafer. The alignment mark includes a groove vertically extending from a main surface of the semiconductor wafer to a bottom surface of the groove, and at least one tin protruding from the bottom surface of the groove. The groove has a rectangular shape with four sidewalls and four inside corners, with each of the four inside corners facing the at least one fin. A minimum distance between the at least one fin and a nearest one of the four inside corners is at least 25 &#x3bc;m.

Method of manufacturing a semiconductor device with epitaxial layers and an alignment mark

An alignment mark in a process surface of a semiconductor layer includes a groove with a minimum width of at least 100 &#x3bc;m and a vertical extension in a range 100 nm to 1 &#x3bc;m. The alignment mark further includes at least one fin within the groove at a distance of at least 60 &#x3bc;m to a closest one of inner corners of the groove.

Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.

Production of an integrated circuit including electrical contact on SiC

A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device.

Method of manufacturing a device by locally heating one or more metalization layers and by means of selective etching

A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.

Semiconductor arrangement with active drift zone

A transistor device includes at least one first type transistor cell including a drift region, a source region, a body region arranged between the source region and the drift region, a drain region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric. A gate terminal is coupled to the gate electrode, a source terminal is coupled to the source region, and a control terminal is configured to receive a control signal. A variable resistor is connected between the field electrode and the gate terminal or the source terminal. The variable resistor includes a variable resistance configured to be adjusted by the control signal received at the control terminal.

Electronic circuit having adjustable transistor device

A semiconductor device includes a first semiconductor die including a normally-off transistor and a second semiconductor die including a plurality of transistor cells of a normally-on GaN HEMT. One of a source terminal and a drain terminal of the normally-off transistor is electrically coupled to a gate terminal of the normally-on GaN HEMT, and the other one of the source terminal and the drain terminal of the normally-off transistor is electrically coupled to one of a source terminal and a drain terminal of the normally-on GaN HEMT. The second semiconductor die further includes a gate resistor electrically coupled between the gate terminal of the normally-off transistor and respective gates of the plurality of transistor cells, and a voltage clamping element electrically coupled between the gate terminal and one of the source terminal and the drain terminal of the normally-on GaN HEMT.

Semiconductor device including a normally-off transistor and transistor cells of a normally-on GaN HEMT

Method of manufacturing a device by locally heating one or more metallization layers and by means of selective etching

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Villach, Austria

Michael Treu