Sige Semiconductor, Inc.

Michael Toner

David George Rahn

Stefan Fulga

John Rogers

Zhan Feng Zhou

Brian Robar

Currently tuner circuits maintain normal power consumption while they are receiving RF signals and do not have provisions therein for disabling portions of their circuitry for reducing of power consumption. For example, during changing of channels, portions of the tuner are not used while the tuner is waiting for channel data. Thus, disabling portions of the circuit while the tuner is waiting for data serves to reduce power consumption of the tuner. Furthermore, tuner power consumption is reduced by determining whether a signal input to the tuner circuit requires amplification or not, or whether linearity in the amplifier can be sacrificed by a reduction in amplifier gain. Thus, a tuner circuit is provided that has control loop circuitry to execute control loops for controlling the gain and linearity of the tuner, as well as power consumption of circuitry therein.

Method of using control loops in a broadband cable tuner

There is a desire to provide a testing method and apparatus that can be successfully integrated into a PLL and PLL-like circuits (e.g. frequency synthesizers, delay lock loops, etc.). It is desirable that the PLL or PLL-like circuit integrated with testing apparatus does not suffer from performance degradations during nominal (mission mode) operation. Furthermore, it is desirable that the PLL and the testing apparatus share the same interface. In order to produce a PLL having integrated testing apparatus, without having the PLL suffer severe performance degradations during nominal operation nor having the combination of the PLL and testing apparatus be unnecessarily large, a modified PLL integrated with testing apparatus is provided.

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Nepean, Canada

Michael Toner