Cypress Semiconductor Corporation

Michael Timothy Moore

Haneef D Mohammed

Pankaj K Jha

James H Lie

Victor So

According to one embodiment, an integrated circuit () includes a programmable portion () and a communication portion (). A programmable portion () may include logic circuits that are configurable by a user. A communication portion () may include one or more circuit blocks designed to perform predetermined serial data communication functions. According to one embodiment, a communication portion () may include a block converter () that can encode/decode input data words into output data words, and a scrambler circuit () for scrambling/de-scrambling data according to a predetermined scrambling polynomial value. Different scrambling polynomial values may be selected from an operation control store () to provide a variety of different scrambling/de-scrambling functions. The inclusion of a communication portion () may reduce the size and/or increase the speed of an integrated circuit over conventional approaches that may synthesize serial data communication functions from programmable logic circuits.

Architecture for efficient implementation of serial data communication functions on a programmable logic device (PLD)

An apparatus generally comprising a circuit and an interface device is disclosed. The circuit may be configured to (i) generate a plurality of test signals to simultaneously stimulate a device and a model of the device during a test and (ii) receive a plurality of model signals generated by the model in response to the test signals. The interface device may be configured to receive a plurality of device signals generated by the device in response the test signals.

Simultaneously driving a hardware device and a software model during a test

An apparatus comprising a wireless transceiver and a programmable logic circuit. The wireless transceiver may be coupled to the programmable logic circuit. The programmable logic circuit may comprise a programmable logic device, a processor, and a memory circuit, implemented in a single integrated circuit package.

Method of programming PLDs using a wireless link

An apparatus comprising one or more look-up-tables (LUTs). The LUTs may be configured to provide logical functions. The one or more LUTs are generally implemented within a multiport memory.

Method of implementing logic functions using a look-up-table

An apparatus comprising one or more logic circuits. The logic circuits may be configured to provide computation. The one or more logic circuits generally comprise dedicated logic within a programmable logic device (PLD).

Configurable dedicated logic in PLDs

According to one embodiment, a programmable logic assembly () may include a nonvolatile memory () may be coupled to an associated volatile programmable logic device (PLD) (). Built-in-self-test (BIST) data () may be stored in a nonvolatile memory () that places the volatile PLD () in a self-test configuration. If a volatile PLD () passes a self-test, user data () may be stored in a nonvolatile memory () that places a volatile PLD () into a user determined configuration.

Method and apparatus for programmable logic device (PLD) built-in-self-test (BIST)

An apparatus including a clock generating circuit and a programmable logic circuit. The clock generating circuit may be configured to generate one or more output signals in response to a reference signal and one or more control signals, wherein the output signals each have a frequency and a phase that are dynamically variable. The programmable logic circuit may be configured to generate one or more of the control signals and receive the one or more output signals.

Architecture of a PLL with dynamic frequency control on a PLD

According to one embodiment, a programmable logic assembly ( ) may include a nonvolatile memory devices ( - and - ) coupled to an associated volatile programmable logic device (PLD) ( ). Each nonvolatile memory device ( - and - ) may store different configuration data for a volatile PLD ( ). Upon a predetermined event, such as powerup or reset, one of the nonvolatile memory devices ( - and - ) may be selected and its configuration data read into a volatile PLD ( ).

Method and apparatus for multiple boot-up functionalities for a programmable logic device (PLD)

A method and system for automatically proactively debugging fitting problems in programmable devices. Automatic fitters are computer programs that place and route circuit resources within a programmable device, e.g., a complex programmable logic device (CPLD) to determine the resources used and timing for a given hardware design. Upon a fitting failure for an IC or hardware design, an embodiment first may identify any specific architectural information, if any, causing the failure and may advise the user including solution recommendations. Second, an embodiment obtains a larger device having the same pin package, if available, or a virtual device, and may perform a second fitting on the hardware design but using this larger device. If this fits properly, then the resulting pin assignment is fixed and a third fitting may be performed on the smaller device with the fixed pin assignment. If this fails, further architectural violations are identified and solution recommendations are given to the user. If there are no larger devices that can be used with the hardware design and/or the third fitting does not obtain a proper result, then an embodiment determines if specific named pins are failing to fit. If these pins are identified, and the user has not locked them down, then they may be allowed to float and fitting is performed once more. If no solution can be reached after the above attempts, then an embodiment informs the user that technical support is required and a history of the fitting attempts may be recorded. A programming file may be generated on a successful fit.

Method and system for proactively debugging fitting problems in programmable logic devices

An I/O cell of a programmable logic device comprising a register, a first multiplexer, a second multiplexer, and a third multiplexer. The first multiplexer may be configured to present one of a plurality of signals to a data input of the register in response to a control signal. The second multiplexer may be configured to select either an output signal from the register or an external input signal in response to the control signal. The third multiplexer may be configured to select one of a number of inputs for presentation as an output signal of the I/O cell in response to the control signal. The register may be configured as an internal register of the programmable logic device when the I/O cell is configured to receive a combinatorial input signal and/or present a combinatorial output signal.

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Santa Clara, CA, United States of America

Michael Timothy Moore