Arm Limited

Michael Thomas Kilpatrick

Peter Guy Middleton

Simon Charles Watt

Guy Larri

Mark Allen Silla

John Stuart Kelly

A cache memory system is described in which a content addressable memory and a cache RAM memory are provided. Each content addressable storage row has an associated hit line and an access enable line . An index decoder is provided for controlling cache replacement and cache maintenance operations. The hit line is used for passing both hit signals to the cache RAM and select signals generated by the index decoder . A gate operating under control of a multiplexer controller controls this dual-use of the hit line in dependence upon a selected mode of operation. In some embodiments a fast block transfer may be performed by loading data from a first address A into the cache memory . A match for the TAG value of the first address A could then be performed and the corresponding hit signal asserted and latched within a latch . Upon a subsequent cycle the latched hit signal can be passed to an access enable line to permit a new TAG value corresponding to a second address B to be written to the content addressable memory . The cached data values from the first address A are now present within the cache memory system associated with a TAG value of the second address B. The dirty bit may be set to ensure that writeback occurs when the data value is removed from the cache memory thereby ensuring data integrity.

Cache memory

An S-R flip-flop circuit is provided using two stacks of gates,with an internal signal Int stored therebetween. Feedback from the output O is used to switch the state of the internal signal Int in a manner that provides an edge-triggered response for at least one of the inputs.

S-R flip-flop circuit

A cache memory 18 is formed of a content addressable memory 20 and a cache RAM 22. The content addressable memory 20 is divided into two or more sections by an AND gate array 28 that serves to selectively either block or unblock the bit lines 26 that supply an input data word to the bit storage and comparison cells 34 of the content addressable memory 20. The generation of match signals for each section is also selectively blocked by preventing the match signal discharge to ground. The match signals from a blocked section are not passed to the RAM 22. The AND gate array 28 and match signal disable may be controlled by the least significant bit of the input data word, higher order bits of the input data word or may be controlled by a bit selected by program control from among the bits of the input data word. When a portion of the bit lines 26 are blocked by the AND gate array 28, then the capacitance of the bit lines 26 that need to be driven is reduced and the number of match lines discharged is halved thereby reducing power consumption.

Bit line and/or match line partitioned content addressable memory

A self-timed data processing circuit and method of operation of such a circuit are disclosed. The circuit comprises a plurality of components, such as memory cells, arranged to generate substantially simultaneously a plurality of first output signals, each representing variable data bits. A timed circuit, which may include a plurality of sense amplifiers, is then arranged to receive the first output signals and to generate second output signals for use in subsequent data processing operations, the information content of the second output signals being dependent on the data bits represented by the first output signals. A subset of the components, such as memory cells storing dirty and valid bits for a cache memory, are arranged to generate first output signals representing data bits that are coded so as to cause at least one of the second output signals generated by the timed circuit to transition from its state prior to the generation of the first output signals. Control circuitry, responsive to the state transition of the at least one second output signal, is then used to generate a timing signal used to control the operation of the timed circuit to provide reduced power consumption. This also enables a reference timing signal to be created to self-time the data processing circuit, without the need to duplicate the critical path of the data processing circuit by using additional reference components.

Data processing apparatus and method for generating timing signals for a

A data processing system incorporating a cache memory 2 and a central processing unit. A storage control circuit 10 is responsive to a programmable partition setting PartVal to partition the cache memory between instruction words and data words in dependence upon whether the central processing unit 4 indicates with signal I/D whether the word to be stored within the cache memory 2 resulted from an instruction word cache miss or data word cache miss. The cache memory array 2 may have a programmably sized portion locked down so that it is not replaced. The selection within the complementary programmable range where overwriting takes place uses a pseudo random selection technique using pseudo random number generator in the form of a linear feedback shift register triggering incrementing of a counter.

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Cherry Hinton, United Kingdom

Michael Thomas Kilpatrick