Texas Instruments Corporation

Michael Thomas DiRenzo

David Patrick Magee

Manish Goel

Mark W Heaton

Robert Allan Neidorff

Michael G Amaro

Brian Ashley Carpenter

Saurav Bandyopadhyay

Thomas Matthew LaBella

A circuit includes a first transistor and a second transistor coupled to the first transistor at a switch node and to a ground node. An estimator circuit receives a first signal to control an on and off state of the first transistor. The estimator circuit generates a second signal to control the on and off state of the second transistor. The second signal has a pulse width based on a pulse width of the first signal. A clocked comparator includes a clock input, a first input, and a second input. The first input receives a voltage indicative of a voltage of the switch node. The second input is coupled to a ground node. The clock input receives a third signal indicative of the second signal. The clocked comparator generates a comparator output signal. The estimator circuit adjusts the pulse width of the second signal based on the comparator output signal.

Adaptive synchronous rectification in a voltage converter

Control logic for producing a digital input to a digital-to-analog converter (DAC) in a power converter system. The control logic selects from among a plurality of slew rates during a transition of an output voltage in response to a change in the desired setpoint, so that the output voltage transition follows a desired nominal slew rate. In an initial interval of the transition, a steeper slew rate than the nominal slew rate is selected by the control logic for the digital input to the DAC, until the digital input to the DAC exceeds the nominal slew rate by a first parameter value. At that point, a slew clamp is applied to advance the digital input at the nominal slew rate. Upon the digital input approaching the setpoint value to within a second parameter value, a flatter slew rate than nominal is applied.

Digital pre-compensation for voltage slewing in a power converter

The present invention provides a packet detector for use with a packet-based wireless receiver employing a receive antenna for P concurrently transmitted streams, where P is at least two. In one embodiment, the packet detector includes a correlation unit coupled to the single receive antenna and configured to provide a correlation function based on P acquisition fields corresponding to the P concurrently transmitted streams. Additionally, the packet detector also includes a pseudo-magnitude calculator coupled to the correlation unit and configured to calculate a packet detection metric based on the correlation function.

Apparatus and method of detection for a packet-based wireless receiver employing multiple, concurrent transmitted streams

A system for synchronizing a wireless receiver is provided. The system includes a first antenna () and a second antenna () to receive wireless signals containing data packets. The system includes one or more analyzer components () operable to determine correlation metrics based on at least a portion of the first received signal and a portion of the second received signal. The system further includes a synchronization component () operable to use the correlation metrics to determine a preferred correlation metric for synchronization by the wireless receiver of the first and second received signals to decode the data packet. A method for synchronizing a receiver of two wireless signals is also provided.

Method of synchronization for packet based, OFDM wireless systems with multiple receive chains

The present invention provides a gain training generator for use with a multiple-input, multiple-output (MIMO) transmitter employing N transmit antennas where N is at least two. In one embodiment, the gain training generator includes a fundamental training encoder configured to provide a basic gain training sequence to one of the N transmit antennas during a time interval to produce a basic gain training waveform having a basic peak-to-average ratio (PAR). Additionally, the gain training generator also includes a supplemental training encoder coupled to the fundamental training encoder and configured to further provide (N&#x2212;1) supplemental gain training sequences to (N&#x2212;1) remaining transmit antennas, respectively, during the time interval to produce supplemental gain training waveforms wherein each has a supplemental PAR substantially equal to the basic PAR.

Scalable gain training generator, method of gain training and MIMO communication system employing the generator and method

This invention comprises an architecture for voltage mode control of a voice coil motor in a hard disk drive. In contrast to conventional current mode control, coil current is not sensed or measured, which simplifies the feedback design with less hardware required in the implementation. Common design methodologies for the square root velocity profile, linear velocity profile and regulator/estimator control system designs can be migrated from the current mode architecture to the voltage mode architecture.

Digital servo control system for a hard disc drive using a voice coil motor in voltage mode

A position sensor includes a stationary platform and a moveable platform. The position sensor further includes at least one beam coupling the moveable platform to the stationary platform. The at least one beam includes piezoresistive material that is positioned tolprovide an indication of a movement of the moveable platform relative to the stationary platform.

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Coppell, TX, United States of America

Michael Thomas DiRenzo