Advanced Micro Devices Corporation

Spansion Llc.

Michael T Wisor

Sherman E Lee

Rita M O'Brien

James R MacDonald

Travis Wheatley

Christopher Gray

Scott E Swanstrom

James A Treadway

Andy Steinbach

Steve Ennis

Dale E Gulick

Scott C Johnson

Drew Jon Dutton

Rodney W Schmidt

Qadeer Ahmad Qureshi

Dan S Mudgett

Lei Cheng

Thomas F Eckert

A first vendor generates one or more files corresponding to an integrated circuit having one or more registers. A content of the files is structured for at least one of: (i) incorporation into a boot code sequence; or (ii) access by the boot code sequence during execution. The boot code sequence is configured to initialize the registers responsive to the content during execution. The first vendor transmits the files to at least one of: (i) a second vendor that develops the boot code sequence; or (ii) a manufacturer of a system that includes the integrated circuit and the boot code sequence. A computer accessible medium comprises instructions which, when executed, generate the files described above and/or comprises the files. A method may include receiving, from the first vendor, the files described above. The content of the files is incorporated into the boot code sequence.

Hardware initialization method that is independent of boot code architecture

A non-volatile memory system is presented having a boot code section, wherein the size of the boot code section may be programmably selected. One embodiment of the non-volatile memory system includes a memory array, a logic unit, a control unit, and a program store. The memory array includes multiple non-volatile memory cells (e.g., flash EEPROM cells). The memory array is divided into memory blocks of equal size. A number of the memory blocks are allocated for boot code storage, forming a boot code section of the memory array. The control unit controls storage of data within and retrieval of data from the memory array. The control unit includes a configuration register having a boot code section size field. The contents of the boot code section size field determine the number of memory blocks making up the boot code section. The logic unit is coupled between the control unit and the memory array, and receives address, data, and control signals from an external source. The logic unit provides the address, data, and control signals to the control unit and to the memory array. The program store stores instructions and data which determine the functionality of the control unit. Commands and configuration data are conveyed to the non-volatile memory system using predetermined sequences of bus write cycles. One embodiment of a computer system includes a central processing unit (CPU), and expansion bus, a memory bus, chip set logic, and the non-volatile memory system.

Non-volatile memory system having a programmably selectable boot code section size

A method and apparatus for concurrent testing of a plurality of microprocessors, each of which may have a different revision, by creating an abstract base class which specifies the names of a plurality of tests, creating a derived class for each revision and defining each of the tests appropriately for each of the derived classes, instantiating an object from one of the derived classes for each of the microprocessors and executing the tests by reference to the objects. A computer system is configured to be coupled to the microprocessors and, upon execution of a debug/test application on the computer system, the revision of each microprocessor is determined and an object is instantiated from the derived class corresponding to the revision. Each object is thereby dynamically bound to the tests defined for the derived class corresponding to the revision, and references to the tests via the objects automatically execute the test code specific to appropriate revision of the microprocessor.

Method for utilizing virtual hardware descriptions to allow for multi-processor debugging in environments using varying processor revision levels

A method and system for testing a plurality of addressing modes in a microprocessor comprising executing a test instruction which is stored in memory, subsequently overwriting the test instruction in memory and then re-executing the test instruction. The test instruction is stored at a memory location which is within a code segment. A data segment is defined to overlap with the code segment and a portion of the test instruction is overwritten by storing data within the overlapping data segment. The overwritten portion of the test instruction identifies the addressing mode of the test instruction and the stored data represents the next addressing mode to be tested. In an x86 architecture, the overwritten portion of the test instruction may comprise a MODR/M byte and an SIB byte, each of which may take on values from 00 to ff (hexadecimal). The addressing modes of the microprocessor may therefore be tested by sequentially incrementing the MODR/M and SIB bytes and executing the test instruction.

Self modifying code to test all possible addressing modes

A method and system for verifying the accuracy of trace data generated by execution of a program on a computer under test, one embodiment of the method comprising scanning the trace data to locate bitmap data corresponding to series of consecutive conditional branches and comparing the number of bits representative of these branches to the number of consecutive conditional branches in the instruction sequence. The trace data includes address entries and bitmap entries. The trace data is scanned in reverse chronological order beginning with the most recent entry to locate an address entry preceding one or more bitmaps which represent a most recent series of conditional branches. Beginning with the instruction at the address contained in the address entry, the program instructions are scanned in program order until a conditional branch is encountered. The branch is counted and the trace data is examined to determine whether the branch was taken and scanning is resumed. The scanning and counting of the conditional branches continues until an instruction which generates a non-bitmap entry is encountered. The number of conditional branches is then compared to the number of bits representative of branches to verify that they are equal. In some embodiments, the target addresses of the branch instructions are also checked to verify that they correspond to the target addresses of the corresponding BTHB entries. Preceding bitmap entries are each checked in this manner until all of the trace data has been verified.

Method for verifying branch trace history buffer information

A method and system for determining the sequence of execution of instructions in a computer under test using trace data generated upon execution of certain ones of the instructions. In one embodiment, the method comprises locating an initial entry in the trace data and scanning the instructions in program order beginning with an instruction indicated by the initial entry. When a branch instruction is encountered, the trace data is examined to determine the subsequently executed instruction. If the branch is unconditional, a corresponding address entry in the trace data indicates the address of the next instruction. If the branch is conditional, a corresponding bitmap entry in the trace data contains a bit which indicates whether the branch was taken. From this bit and the instructions themselves, the next instruction is determined. The bitmap entry contains a series of bits, each of which can indicate whether a conditional branch was taken, so that a single bitmap entry can represent a series of conditional branches.

Mechanism to determine actual code execution flow in a computer

A hardware-based system for configuring a CPU and chip set logic of a computer system to allow data transfers on both the rising and falling edges of a bus clock signal. The CPU and chip set logic each include bus communication circuitry for transferring data, a storage unit, and a configuration circuit. The contents of the storage unit determine whether the respective bus communication circuitry transfers data on only one or on both clock edges. Initially, the bus communication circuits transfer data on only one clock edge. The configuration circuits of the CPU and chip set logic are connected by a single signal line and participate in a serial exchange of signals over the single signal line. The configuration circuits modify the contents of the respective storage units dependent upon an outcome of the serial exchange of signals. The configuration circuit of the CPU initiates the exchange of signals, transmitting a query signal. Upon receiving the query signal, the chip set logic configuration circuit transmits a response signal and modifies the contents of the chip set logic storage unit such that the chip set logic bus communication circuitry transfers data on both clock edges. Upon receiving the response signal from the chip set logic, the CPU configuration circuit modifies the contents of the CPU storage unit such that the CPU bus communication circuitry transfers data on both clock edges. As a result, data transfers on both clock edges are implemented within the computer system.

Hardware-based system for enabling data transfers between a CPU and chip

A power management unit is provided that includes a plurality of configuration registers for storing configuration information to set various operational parameters of the power management unit. A program register is mapped within the configuration space of the computer system and is utilized to store a value which sets the I/O address of the index register. The program register is written during the initialization of the power management unit, and may be associated with a predetermined default value. Once the program register has been set with a value indicating the I/O address of the index register, accesses to the configuration registers are achieved by first writing an offset value to the index register. Subsequently, configuration data may be written into or read out of a designated configuration register by executing an appropriate cycle to the address of the configuration data register, which may be mapped one word location beyond that of the index register. As a result of the programmable index register, the addresses of the index register and the configuration data register within the I/O space of the computer system may be specified via software, thus allowing the system designer greater flexibility with respect to the selection of other peripheral devices incorporated within the computer system.

Power management unit including a programmable index register for

A shared interface to a non-volatile memory including a first storage area for BIOS and a second storage area (e.g., for multimedia data) provides an integrated configuration which saves the cost and space of duplicating memory elements to support multiple data and program types in personal computers. The BIOS information is shadowed from the non-volatile memory to a second memory (e.g., a PC main memory). Thereafter, the BIOS information is accessed in the second memory and the information of the second storage area is accessed via the shared interface. The storage may be integrated upon personal computer system boards without a degradation in performance or an increase in pin count of the board memory because the same pins are used at different times for different memory portions. Accordingly, a storage system is provided to meet the demands of increasing storage requirements without a corresponding increase in cost, space or performance.

Bios memory and multimedia data storage combination

A method for testing the functioning of a non-cacheable region within a cache having a cache controller programmed with a write-back write policy and a non-cacheable region included in an image memory region corresponding to a physical memory region. A first data pattern is written to the cache tagged at a first addressable location of a cacheable region in the physical memory region. A second data pattern is written to the cache tagged at a second addressable location in the image memory region contained within both the non-cacheable region and the cacheable region and corresponding to the first addressable location. The data stored in the cache and tagged at the first addressable location and corresponding to the non-cacheable region only of the second addressable location is read to determine whether the first data pattern remains in the cache thereby indicating that the non-cacheable region is functioning correctly. The data stored and tagged at a third addressable location in the physical memory region and corresponding to the cacheable region only of the second addressable location in the image memory region is read to determine whether the second data pattern remains in the cache tagged at the third addressable location thereby indicating that the non-cacheable region is functioning correctly and that the memory size of the non-cacheable region is correct.

Method for testing the non-cacheable region functioning of a cache

A computing system and bus bridge in which the bus bridge includes a buffer pool wherein the storage buffers contained in the buffer pool may be allocated as post buffers or fetch buffers in response to appropriate requests from the bus bridge. In the preferred embodiment, the bus bridge includes a buffer pool control unit adapted to temporarily allocate any of the plurality of storage buffers as either a post buffer or a fetch buffer depending upon the system requirements. Broadly speaking, the present invention contemplates a computing system including a first component connected to a first bus, a second component connected to a second bus, and a bus bridge connected to a first and second busses. The bus bridge includes a buffer pool comprised of a plurality of storage buffers and a buffer pool control unit that is capable of temporarily allocating at least one of the storage buffers as either a post buffer or a fetch buffer in response to system requirement. Preferably, each storage buffer includes corresponding tag information for identifying an origin or destination location within a main memory of the data associated with the storage buffer. In one embodiment, each of the plurality of storage buffers includes corresponding allocation information used by the buffer pool control unit for the temporary allocation of the storage buffers. In a presently preferred embodiment, the allocation information includes an available bit indicative of whether the storage buffers available for allocation and a post/fetch bit indicative of whether an unavailable storage buffer is currently allocated as a post buffer or as a fetch buffer. The allocation information is accessible by the buffer pool control unit and is used by the buffer pool control unit for temporarily allocating the storage buffers.

Allocatable post and prefetch buffers for bus bridges

A system and method for providing a microprocessor with a software accessible serial number. A plurality of programmable fuses on the processor are encoded with a value representative of a serial number. Circuitry is provided on the processor for transferring the value encoded on the programmable fuses to a machine specific or general purpose register or storage device. The machine specific or general purpose register or storage unit is software accessible.

System and method for providing microprocessor serialization using

A method and apparatus for providing a microprocessor serial number. A small, nonvolatile random access memory is packaged with the CPU die to provide a storage space for a CPU serial number which can be programmed before leaving the factory. Both the CPU die and the nonvolatile RAM die reside within the cavity of the package. Connection between the two die is provided by conventional wire bonding.

Growing community of inventors

Austin, TX, United States of America

Michael T Wisor