Honeywell International Inc.

Honeywell G.m.b.h.

Michael T Johnson

Walter W Heikkila

Toan Dinh Nguyen

A level shift circuit for providing predictable outputs when VDDH is powering up and minimizing DC current when VDDL is powering up. The level shift circuit may have a control circuit that includes a first inverter with an input coupled to VDDL, one or more diodes coupled between the first inverter and its powering voltage supply, a second inverter coupled to an output of the first inverter (optionally coupled to its voltage supply via one or more diodes), a third inverter coupled to an output of the second control inverter, an NMOS transistor coupled to an output of the third inverter that forces the output of the level shift circuit to the ground voltage when enabled, and a PMOS transistor coupled to an output of the third inverter that disconnects a portion of the level shift circuit, and thus the output of the level shift circuit, from VDDH when disabled.

Level shift circuit with power sequence control

A power distribution system for a semiconductor die includes bonding pads located adjacent to and connected to power busses with connections between the bonding pads providing a parallel path for current. Connections may be provided by stitch bonds, by conductors within a substrate or by other means.

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Plymouth, MN, United States of America

Michael T Johnson