Iowa State University Research Foundation Inc

Michael T Frederick

Arun Somani

A method of creating logic chains in a Boolean network of a reconfigurable fabric is provided. The method includes creating a plurality of logic chains in the reconfigurable fabric. The plurality of logic chains include at least one arithmetic logic chain and at least one non-arithmetic logic chain. A method of creating logic chains in a Boolean network of a look-up table based FPGA includes: applying a labeling method by (a) finding a depth increasing node, (b) isolating the depth increasing node, and (c) finding minimum height cuts; mapping to generate a mapping solution using the minimum height cuts; applying a duplication method to implement an exclusivity constraint; and arranging connections in the look-up table based FPGA using the logic chains.

Depth-optimal mapping of logic chains in reconfigurable fabrics

A reconfigurable device includes an arrangement of a plurality of cells and routing resources for transmitting signals between the cells. The plurality of cells comprises carry-select reuse cells, each of the carry-select reuse cells configured to provide for performing non-arithmetic operations using a reuse arithmetic carry chain interconnecting adjacent cells.

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Colorado Springs, CO, United States of America

Michael T Frederick