International Business Machines Corporation

Micron Technology Incorporated

Seagate Technology Incorporated

Michael T Brady

Joan LaVerne Mitchell

Jennifer Quirin Trelewicz

Tomasz J Nowicki

Marco Martens

Timothy James Trenary

Robert J German

Chee Hock Ngo

Kok Hua Tan

David A Hartman

Larry Joseph Koudele

Carl Robert Bildstein

David L Miller

Gary D Hamor

Arthur Kenneth Ford

William A Marcus

Jennifer Quinn Trelewicz

Bradley S Ramsey

Mari C Brady

Erich P Meier

A system includes a memory component and a processing device operatively coupled with the memory component. The processing device performs a test of the memory component by generating an error correction code (ECC) value for an initial operation of the test based on an address in the memory component on which the initial operation of the test is performed, generating ECC values for subsequent operations of the test, and reporting the ECC value generated for the last of the subsequent operations of the test in an event log. The ECC value for each respective subsequent operation of the test is generated based on an address in the memory component on which that respective subsequent operation of the test is performed, and the ECC value generated for the operation of the test that was performed immediately before that respective subsequent operation.

Performing memory testing using error correction code values

A request to generate one or more random values can be received. In response to receiving the request to generate the one or more random values, a first read operation can be performed on a memory cell of the memory component to retrieve first data and a second read operation can be performed on the same memory cell of the memory component to retrieve second data. The first data can be compared with the second data to identify a difference between the first data and the second data. The difference can be associated with a noise characteristic of the memory cell. The one or more random values can be generated based on the difference between the first data and the second data that is associated with the noise characteristic of the memory cell.

Generating a random value based on a noise characteristic of a memory cell

A method to perform an on demand refresh operation of a memory sub-system is disclosed. The method includes identifying a temporal attribute of user data stored in the memory component, upon determining that the identified temporal attribute satisfies a time condition, providing an indication whether a refresh operation of the user data improves performance of the memory component, receiving an indication to perform the refresh operation of the memory component, and responsive to a time between the refresh operation and a previously performed refresh operation not satisfying a threshold criterion, refraining from performing the refresh operation of the memory component.

Performing an on demand refresh operation of a memory sub-system

A method to perform an on demand refresh operation of a memory sub-system is disclosed. The method includes sending an initial translation map to a host system coupled to a memory component, receiving, from the host system, a modified translation map, and performing, by a processing device, a refresh operation of the memory component using the modified translation map.

A processing device of a memory device test resource detects that a memory sub-system has engaged with a first memory sub-system interface port and a second memory sub-system interface port of the memory device test resource. The processing device causes a power supply signal to be transmitted from the memory device test resource to the memory sub-system via the first memory sub-system interface port. The processing device identifies a test to be performed for a memory device of the memory sub-system, where the test includes one or more test instructions to be executed in performance of the test. The processing device causes the one or more test instructions to be transmitted from the memory device test resource to the memory sub-system via the second memory sub-system interface port, where the test is performed by the one or more test instructions executing at the memory sub-system.

Transmitting data and power to a memory sub-system for memory device testing

A temporal attribute of user data stored in a memory component is identified. It is determined that the identified temporal attribute satisfies a time condition. An indication is provided whether a refresh operation of the user data improves performance of the memory component. A user input is received indicating to perform the refresh operation of the memory component. The refresh operation of the memory component is performed.

A method comprises creating calibration data using a first control circuitry of an apparatus, replacing the first control circuitry with a second control circuitry in the apparatus, and operating the apparatus with the second control circuitry using the calibration data. As an example, the apparatus may be a disc drive. The second control circuitry may be substantially similar to the first control circuitry such that calibration measurements using the first control circuitry are applicable to the second control circuitry. The first control circuitry may be included in a circuit board that is replaced with a second circuit board including the second control circuitry. In an exemplary embodiment, the second circuit board may include different and/or additional components relative to the first circuit board, such as integrated video inputs and/or video control circuitry.

Disc drive circuitry swap

Fast transforms that use early aborts and precision refinements are disclosed. When to perform a corrective action is detected based upon testing the incremental calculations of transform coefficients. Corrective action is then performed. The corrective action includes refining the incremental calculations to obtain additional precision and/or aborting the incremental calculations when the resulting numbers are sufficient.

Faster transforms using early aborts and precision refinements

Methods and systems for efficient scaling in the transform domain are provided when transform coefficient data is provided as an input to a data processing system, comprising generating a first matrix from transform coefficient data; zeroing out a row or column of, or inserting a row or column of zeros into, the first matrix; generating a second matrix by applying a one-dimensional inverse transform to the first matrix with the zeroed-out at least one row, the at least one column, the inserted at least one row of zeros or the at least one column of zeros; generating a third matrix by regrouping the second matrix; generating a combined matrix by applying a forward transform to the third matrix; and the data processing system scaling the data represented by the transform coefficient data by applying the combined matrix to the transform coefficient data.

Efficient scaling in transform domain

A method and system for efficient scaling in the transform domain, wherein transform coefficient data is provided as an input to a data processing system and scaled in the transform domain by application of a combined matrix. Some embodiments utilize discrete cosine transform data. One embodiment of the invention generates a combined matrix for one-dimensional scaling by selecting a rational scaling factor and matrix dimension value, generating a matrix with some zero values, applying a one-dimensional inverse transform, regrouping, and applying a one-dimensional forward transform. One application of the invention performs up-scaling operations, and another performs down-scaling operations. The invention also provides for two-dimensional scaling by selecting horizontal and vertical scaling parameters and generating first and second combined matrices responsive to the parameters and combining them into a single combined matrix. The invention may also incorporate a predetermined cost function.

A system and method for processing multiple arbitrary sized data elements in a register. A method of the invention comprises the steps of: creating a mask register that defines a set of arbitrary sized segments for a register; storing a plurality of arbitrary sized data elements in a segmented data register arranged in accordance with the mask register, wherein the arbitrary sized data elements are sign extended; simultaneously operating on each of the of the data elements in the segmented data register to generate a set of resulting data elements in response to a machine instruction, wherein the resulting data elements depend on each other; and unpacking the resulting data elements to provide a plurality of arbitrary sized results that are independent of each other.

System and method for using hardware assist functions to process multiple arbitrary sized data elements in a register

A compiler for data processing outputs lower-level code for packing multiple signed data elements per register into a processor's registers using the rules set forth herein, and when executed, the code simultaneously operates on the elements in a register in a single cycle using the same operand. The elements can be independent of each other as defined by compiler directives, and the sizes of the elements in a register can differ from each other. Moreover, a relatively large element can be split across multiple registers. In an exemplary application, a data stream representing two images can be simultaneously processed using the same number of registers as have been required to process a single image. Or, a single image can be processed approaching N-times faster, where N is the number of elements per register. In any case, the present invention results in a significant increase in processing efficiency.

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Loveland, CO, United States of America

Michael T Brady