Hrl Laboratories, LLC

Other

Michael T Antcliffe

Adele E Schmitz

Ivan Milosavljevic

Ming Hu

Joel C Wong

Jeong-Sun Moon

Michael Delaney

Robert M Grabar

Lorna Hodgson

A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer; and forming a tri-layer gate having a gate foot in the first opening, the gate foot having a first width, a gate neck extending from the gate foot and extending for a length over the dielectric passivation layer on both sides of the first opening, the gate neck having a second width wider than the first width of the gate foot, and a gate head extending from the gate neck, the gate head having a third width wider than the second width of the gate neck.

Miniature field plate T-gate and method of fabricating the same

A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer, and forming a tri-layer gate having a gate foot in the first opening, a gate neck extending from the gate foot, and a gate head extending from the gate neck. The gate foot has a first width, and the gate neck has a second width that is wider than the first width. The gate neck extends for a length over the dielectric passivation layer on both sides of the first opening. The gate head has a third width wider than the second width of the gate neck.

In various embodiments, a tiered gate structure transistor is provided including a source, a drain, and a gate between the source and the drain. The tiered gate structure transistor including a gate foot having a top portion and sidewalls. A gate head is attached to the top portion of the gate foot. A passivation layer extends along and directly contacts an uppermost surface of the source, and extends along and directly contacts an uppermost surface of the drain, the passivation layer surrounds the sidewalls of the gate foot such that the top portion is not covered by the passivation layer and such that the passivation layer surrounding the sidewalls supports the gate head.

Passivated tiered gate structure transistor

In one embodiment, a tiered gate device is provided including a source, a drain, and a gate foot therebetween. A gate head is attached to the gate foot. A source extension extends from on an uppermost surface of the source toward the gate foot along the substrate. In some embodiments a drain extension extends from on and uppermost surface of the drain toward the gate foot along the substrate.

Tiered gate device with source and drain extensions

In one embodiment, a tiered gate structure is provided having a substrate including a source, a drain and a gate thereon. The gate includes an elongated gate foot having a first deposition gate material extending from the substrate, the elongated gate foot having a top portion distal from the substrate. The gate head has a second deposition gate material and includes an elongated portion extending downward from the gate head to connect to the top portion of the elongated gate foot.

Tiered gate structure devices

A method for fabricating a tiered structure includes forming a gate on a semiconductor substrate. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening through it to define the gate foot over the substrate. After forming the gate foot, the gate foot mask is stripped and a passivation layer is formed over the gate foot and the substrate. A gate head mask is formed over the gate foot with the gate head mask exposing a portion of the passivation layer on a top portion of the gate foot. The portion of the passivation layer on the top portion of the gate foot is removed to expose the top portion of the gate foot. A gate head is formed on the top portion of the gate foot using the gate head mask. A lift-off process is performed, removing the gate head mask.

Passivated tiered gate structure transistor and fabrication method

In one embodiment, a tiered gate device is provided including a source, a drain, and a gate foot therebetween. A gate head is attached to the gate foot. A source extension extends from on the source toward the gate foot along the substrate. In some embodiments a drain extension extends from on the drain toward the gate foot along the substrate.

In one implementation, a method for fabricating a tiered structure is provided, which includes forming a source and a drain on a substrate with a gate formed therebetween. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening through it to define the gate foot over the substrate. After forming the gate foot, the gate foot mask is stripped. A gate head mask is formed over the gate foot with the gate head mask exposing a top portion of the gate foot. A gate head is formed on the top portion of the gate foot using the gate head mask. A lift-off process is performed, removing the gate head mask.

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Malibu, CA, United States of America

Michael T Antcliffe