Avid Technology Limited

Data General Corporation

Netezza Corporation

IBM International Group Bv

Michael Sporer

Peter Zawojski

James Robert Hamilton

James Marriot Guyer

Katherine H Cornog

William F Baxter

David L Keating

Sharon Miller

Robert G Gelinas

Pat J Weiler

Rob P Valentine

Liz M Truebenbach

Phil J Roux

Jeff S Kimmell

Michael F Hunt

Tom V Radogna

Dan R Huck

Rob J Pike

Simon N Yeung

Andrea Heyda

Doug J Tucker

Art A Sherman

Barry E Gillott

Joseph Cox

Mark H Kline

Barry M Zane

Foster D Hinshaw

David L Meyers

William K Stewart

Raymond J Andraka

John Yates

An approach for providing compression of a database table that uses a compiled table algorithm (CTA) that provides leverage. Data within any given column in adjacent rows is often the same as or closely related to its neighbors. Rather than storing data in each column of each row as a specific integer, floating point, or character data value, a field reconstruction instruction is stored that when executed by a decompression engine can reconstruct the data value. The field reconstruction instruction may be bit granular and may depend upon past history given that the data compression engine may preserve state as row data is streamed off a storage device.

Technique for compressing columns of data

A programmable streaming data processor that can be programmed to recognize record and field structures of data received from a streaming data source such as a mass storage device. Being programmed with, for example, field information, the unit can locate record and field boundaries and employ logical arithmetic methods to compare fields with one another or with values otherwise supplied by general purpose processors to precisely determine which records are worth transferring to memory of the more general purpose distributed processors. The remaining records arrive and are discarded by the streaming data processor or are tagged with status bits to indicate to the more general purpose processor that they are to be ignored. In a preferred embodiment, the streaming data processor may analyze and discard records for several reasons. The first reason may be an analysis of contents of the field. Other reasons for record blocking may have to do with tagging records that are to be visible to particular users depending upon a series of concurrent transactions.

Intelligent storage device controller

Random access to arbitrary fields of a video segment compressed using both interframe and intraframe techniques is enhanced by adding state information to the bitstream prior to each intraframe compressed image to allow each intraframe compressed image to be randomly accessed, by generating a field index that maps each temporal field to the offset in the compressed bitstream of the data used to decode the field, and by playing back segments using two or more alternatingly used decoders. The cut density may be improved by eliminating from the bitstream applied to each decoder any data corresponding to bidirectionally compressed images that would otherwise be used by the decoder to generate fields prior to the desired field.

Computer system and process for capture, editing and playback of motion video compressed using interframe and intraframe techniques

Random access to arbitrary fields of a video segment compressed using both interframe and intraframe techniques is enhanced by adding state information to the bitstream prior to each intraframe compressed image to allow each intraframe compressed image to be randomly accessed by generating a field index that maps each temporal field to the offset in the compressed bitstream of the data used to decode the field, and by playing back segments using two or more alternatingly used decoders. The cut density may be improved by eliminating from the bitstream applied to each decoder any data corresponding to bidirectionally compressed images that would otherwise be used by the decoder to generate fields prior to the desired field.

Computer system and process for capture editing and playback of motion

A digital motion video processing circuit can capture, playback and manipulate digital motion video information using the system memory of a computer as a data buffer for holding compressed video data from the circuit. The system memory may be accessed by the circuit over a standard bus. A controller in the circuit directs data flow between an input/output port which transfer a stream of pixel data and to the standard bus. The controller directs data to and from either the standard bus or the input/output port through processing circuitry for compression, decompression, scaling and buffering. The standard bus may be a peripheral component interconnect (PCI) bus. The motion video processing circuit has a data path including pixel data and timing data indicative of a size of an image defined by the pixel data. The timing data is used and/or generated by each component which processes the pixel data, thereby enabling each component to process the pixel data without prior knowledge of the image format. By having processors for handling two compression formats for motion video data connected to this data path, conversion between compression formats, such as between MPEG to Motion JPEG, can be performed.

Motion video processing circuit for capture, playback and manipulation

A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency. The motherboard also includes GTL backpanel interface logic, system clock generation and distribution logic, and local resources including a micro-controller for system initialization. A crossbar switch connects the various logic blocks together. A fully loaded motherboard contains 2 JP daughterboards, two PCI expansion boards, and up to 512 MB of main memory. Each daughterboard contains two 50 MHz Motorola 88110 JP complexes, having an associated 88410 cache controller and 1 MB Level 2 Cache. A single 16 MB third level write-through cache is also provided and is controlled by a third level cache controller.

Bus arbitration system for multiprocessor architecture

Symmetric multiprocessing computer with non-uniform memory access

Motion video processing circuit for capture playback and manipulation of

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Wellesley, MA, United States of America

Michael Sporer