Intel Corporation

Michael Spica

Tak Ming Mak

Michael J Tripp

Hehching Harry Li

Md Rezwanur Rahman

Methods and apparatus to test memories, such as, for example, caches of processors, are disclosed. In one aspect, an apparatus may include a pseudo random address generation unit, such as, for example, including a linear feedback shift register, to generate pseudo random memory addresses, and a deterministic data generation unit, such as, for example, including a state machine, to generate deterministic data to be written to the pseudo random memory addresses. Computer systems and other electronic systems including such apparatus are also disclosed.

Testing memories

An apparatus and method for testing memory cells comprising coupling a first and a second memory cell to a first and a second bit lines, respectively, reading data from the first and second memory cells through the first and second bit lines, and comparing the voltage levels of the first and second bit lines.

Memory cell structural test

An apparatus and method for testing an address decoder and word lines of a memory array comprised of connecting a signature analyzer to the word lines emanating from an address decoder, setting a clock used to trigger the latching of the states of the word lines by the signature analyzer, transmitting an address to the address decoder to be decoded, and triggering the signature analyzer to latch the state of the word lines.

Memory addressing structural test

A circuit test method and apparatus uses a spectral characteristic of a supply voltage to detect defects within a device under test (DUT). The spectral characteristic of the supply voltage is preferably measured as the DUT undergoes a predetermined operational sequence. The measured spectral characteristic value is then compared to a predetermined test criterion to determine whether the DUT is likely to include a defect.

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Hillsboro, OR, United States of America

Michael Spica