International Business Machines Corporation

Globalfoundries Inc.

Michael Sperling

Erik English

Paul David Muench

Daniel Mark Dreps

Pawel Owczarczyk

Seongwon Kim

Akil Khamisi Sutton

Frank David Ferraiolo

Jieming Qi

John Francis Bulzacchelli

Miguel E Perez

Peilin Song

James David Strom

Donald W Plass

Grant Paul Kesselring

George E Smith, Iii

Anuja Sehgal

Kangguo Cheng

Geng Wang

Michael Stephen Floyd

John Edward Barth, Jr

David John Krolak

David Michael Friend

Zeynep Toprak Deniz

Hector Saenz

Dureseti Chidambarrao

Terence B Hook

Daniel Joseph Friedman

Robert K Montoye

Jente Benedict Kuang

William Robert Reohr

William Eric Hall

Fadi Hikmat Gebara

Larry Wissel

Michael B Spear

Mangal Prasad

Charlie Chornglii Hwang

Chad Andrew Marquart

Joel T Ficke

Douglas J Malone

Kennedy K Cheruiyot

Zeynep Toprak-Deniz

Erik S Unterborn

Ann H Chen

Birgit Schubert

Michael R Whalen

Method and apparatus for transferring a data signal including receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal by a first inverted data input of the transmitter multiplexer; counting, by a first counter, a clock signal; transmitting, by the first counter and in response to the first counter counting a threshold number of clock cycles, a first selection signal to a first selection signal input of the transmitter multiplexer; and alternately transmitting, in response to the first selection signal and by a first digital data signal output of the transmitter multiplexer, the digital data signal and the inverted digital data signal as the transmitter output signal to a receiver, the receiver and the digital data signal output operably coupled to a data link.

Communication systems for power supply noise reduction

Method and apparatus for transferring a data signal including receiving a digital data signal by a first input of a multiplexer of a transmitter operably coupled to a data link; transmitting, by a digital data signal output of the multiplexer, the digital data signal to a receiver that is operably coupled to the data link; receiving, by a selection signal input of the multiplexer, a first selection signal that indicates an idle mode for the transmitter; receiving, by a second input of the multiplexer, a patterned data signal; and transmitting, by the digital data signal output and in response to the first selection signal, the patterned data signal to the receiver.

An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.

Quadrature circuit interconnect architecture with clock forwarding

An enhanced quadrature receive serial interface circuit and methods are provided for calibrating the quadrature receive serial interface circuit. A quadrature receive serial interface circuit comprises a first phase rotator and a second phase rotator generating quadrature clocks of identical frequency. Calibration of the quadrature receive serial interface circuit uses a pseudo random bit sequence (PRBS) received by the quadrature receive serial interface circuit. For calibration, one-half of the received PRBS bits are sampled and the phase rotator generating in-phase 0° and 180° clock signals is adjusted to center the data eye for the sampled half of the PRBS bits. Then all data bits (even and odd data bits) of the received PRBS bits are sampled and the phase rotator generating quadrature phase 90° and 270° clock signals is adjusted to center the data eye of all data bits of the PRBS bits to complete calibration.

Calibrating a quadrature receive serial interface

Aspects of the invention include a circuit having a power header configured to couple to a power supply and to provide an output voltage. A sense circuit is coupled to the power header to receive the output voltage, the sense circuit including a replica voltage circuit coupled to a replica power header circuit and a transistor, the replica voltage circuit being configured to provide a replicated output voltage in accordance with the output voltage, the replica power header circuit being configured to couple to the power supply and the replicated output voltage to generate a replica current, the transistor being configured to deliver the replica current.

Current measurement in power-gated microprocessors

Aspects of the invention include forming a semiconductor device. Gates are formed in a first direction over fins, the gates including gate material, the fins being formed in a second direction. Fin interconnects are formed in the first direction over the fins. A dielectric material is formed on the fins, and capacitor interconnects are formed over portions of the dielectric material in the first direction over the fins.

FEOL interconnect used as capacitance over fins instead of gates

A phase locked loop having a charge pump is described. The charge pump has circuitry to select a mode for each semiconductor chip from a plurality of modes to enhance yield. Nine unique modes are defined from which a selection is made for each chip. The selected mode mitigates effects of device mistracking anomalies for each chip. A method is provided to show how the modes are determined and prioritized.

Multi-mode design and operation for transistor mismatch immunity

Aspects of the invention include a first voltage sensitive circuit including first transistors, the first transistors being coupled together so as to be operatively coupled to a first current source. A second voltage sensitive circuit includes second transistors, the second transistors being coupled together so as to be operatively coupled to a second current source, the first voltage sensitive circuit being coupled to the second voltage sensitive circuit to form a delay chain, the first and second current sources being responsive to changes in voltage of a power supply according to a voltage reference. A voltage sensitive current reference module is coupled to the first and second current sources and configured to supply the voltage reference to the first and second current sources, the voltage sensitive current reference module being responsive to changes in the voltage of the power supply.

Voltage sensitive current circuit

Aspects of the invention include a circuit having a power supply sensitive delay circuit, a variable delay circuit coupled to the power supply sensitive delay circuit, a delay line coupled to the variable delay circuit, and a logic circuit coupled to the delay line.

Droop detection using power supply sensitive delay

Aspects of the invention include a circuit having a two-stage amplifier coupled to a transistor array and to a comparator, the transistor array being configured to provide an output to a load, the transistor array including transistors. The circuit includes a controller coupled to the comparator and to the transistor array, the two-stage amplifier being configured to modulate a current density in the transistor array via gate terminals of the transistors, wherein, by using the comparator and the controller, the two-stage amplifier is configured to modulate a number of the transistors that are to couple to the load.

Digitally assisted low dropout (LDO) voltage regulator

Aspects of the invention relate to an apparatus having a transmission gate coupled to a delay element and including a first transistor and a second transistor. A first node is coupled to a first gate of the first transistor, a first current source, and a first resistive element, an opposite end of the first resistive element being coupled to a ground potential. A second node is coupled to a second gate of the second transistor, a second current source, and a second resistive element, an opposite end of the second resistive element being coupled to a power supply.

Voltage starved passgate with IR drop

Techniques for a slope detector for voltage droop monitoring are described herein. An aspect includes receiving an input voltage by a circuit. Another aspect includes producing, by the circuit, a filtered offset voltage based on the input voltage. Another aspect includes determining whether the input voltage is lower than the filtered offset voltage. Yet another aspect includes, based on the input voltage being lower than the filtered offset voltage, indicating an imminent voltage droop condition in the input voltage.

Slope detector for voltage droop monitoring

Aspects of the invention include a process for receiving data and a first clock signal of a first chip and a second clock signal of a second chip, the data being received on a data path and the first clock signal being received on a clock signal path, and determining that the first clock signal is arriving before the second clock signal by a difference quantity. Also, the process includes adding delay to the data path and the clock signal path according to the difference quantity.

Early mode protection for chip-to-chip synchronous interfaces

Aspects of the invention include a circuit including a power circuit having an amplifier, a resistor, a current source, and a first node, one end of the resistor being configured to couple to a power supply, the first node being coupled to an opposite end of the resistor, a first input terminal of the amplifier, and the current source. A voltage sensitive circuit includes a logic gate coupled to both a second input terminal of the amplifier and an output terminal of the amplifier at a second node.

Voltage sensitive delay

A technique relates to a digital phase locked loop (DPLL) including a digitally controlled oscillator (DCO), the DCO having delay elements and a current fill factor corresponding to a proportion of the delay elements in operation. A voltage regulator controller is operable to obtain a result of a comparison between a predefined fill factor and the current fill factor, the voltage regulator controller being operable to adjust voltage supplied to the DCO based on the result, the predefined fill factor indicating a predetermined proportion of the delay elements to be in operation.

Maintaining a digitally controlled oscillator at an ideal state by changing the voltage supply

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Poughkeepsie, NY, United States of America

Michael Sperling