Infineon Technologies Ag

Qimonda Ag

Qimonda Flash Gmbh

Infineon Technologies LLC

Infenion Technologies Ag

Michael Specht

Franz Hofmann

Richard Johannes Luyken

Wolfgang Roesner

Erhard Landgraf

Wolfgang Rösner

Josef Willer

Johannes Luyken

Thomas Schulz

Dirk Manger

Christoph Friederich

Doris Keitel-Schulz

Johannes Kretz

Andrew Graham

Lothar Risch

Franz Kreupl

Nicolas Nagel

Thomas Mikolajick

Roman Knoefler

Wolfgang Hönlein

Lars Dreeskornfeld

Martin Städele

Martin Staedele

Till Schloesser

Volker Lehmann

Detlev Richter

Till Schlösser

Stephan Riedel

Wolfgang Rosner

Lars Bach

Klaus Knobloch

Thomas Melde

Gert Koebernik

Steffen Meyer

Jan Gutsche

Eike Ruttkowski

Kenny Oisin

Holger Moeller

Doris Keitel Schulz

Joseph Willer

Guerkan Ilicali

Ulrich Dorda

Lothar Risoh

Florian Beug

Massimo Atti

An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.

Integrated circuit with floating-gate electrodes including a transition metal and corresponding manufacturing method

A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.

Semiconductor memory device

In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

Integrated circuits having a contact region and methods for manufacturing the same

An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack and a gate dielectric on a first surface section of a main surface of a semiconductor substrate, and a second gate stack including a memory layer stack on a second surface section. A first pattern is transferred into the first gate stack and a second pattern into the second gate stack.

Integrated circuit including a first gate stack and a second gate stack and a method of manufacturing

An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree.

Integrated circuit with an active area line having at least one form-supporting element and corresponding method of making an integrated circuit

A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.

Memory cell arrangements

An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.

Integrated circuit including a gate electrode

A method for forming trenches on a surface of a semiconductor substrate is described. The method may include: etching a first plurality of trenches into the surface of the semiconductor substrate; filling the first plurality of trenches with at least one material; and etching a second plurality of trenches into every second trench of the first plurality of trenches. Furthermore, a method for forming floating-gate electrodes on a semiconductor substrate and an integrated circuit is described.

Method for forming trenches on a surface of a semiconductor substrate

Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.

Integrated circuits and methods of manufacturing thereof

The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.

Vertically integrated field-effect transistor having a nanostructure therein

Embodiments of the invention relate generally to a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement, an integrated circuit, a cell arrangement, and a memory module. In an embodiment of the invention, a method for manufacturing an integrated circuit having a cell arrangement is provided, including forming at least one semiconductor fin structure having an area for a plurality of fin field effect transistors, wherein the area of each fin field effect transistor includes a first region having a first fin structure width, a second region having a second fin structure width, wherein the second fin structure width is smaller than the first fin structure width. Furthermore, a plurality of charge storage regions are formed on or above the second regions of the semiconductor fin structure.

Integrated circuit having a Fin structure

The present invention provides a FinFET transistor arrangement produced using a method with the steps: providing a substrate (); forming an active region () on the substrate a fin-like channel region (&#x2033;). Formation of the fin-like channel region (&#x2033;) has the following steps: forming a hard mask (S-S) on the active region (); anisotropic etching of the active region () using the hard mask (S-S) forming STI trenches (G-G) having an STI oxide filling (); polishing-back of the STI oxide filling (); etching-back of the polished-back STI oxide filling (); selective removal of components of the hard mask forming a modified hard mask (S-S); anisotropic etching of the active region () using the modified hard mask (S-S) forming widened STI trenches (G-G'), the fin-like channel regions (&#x2033;) of the active region () remaining for each individual FinFET transistor.

Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement

Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.

Integrated circuits; methods for manufacturing an integrated circuit; memory modules; computing systems

Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.

Method for producing a substrate

A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.

Semiconductor memory component with body region of memory cell having a depression and a graded dopant concentration

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Munich, Germany

Michael Specht