Stmicroelectronics (grenoble 2) Sas

Stmicroelectronics S.r.l.

Stmicroelectronics S.a.

Stmicroelectronics (alps) Sas

Stmicroelectronics (grand Ouest) Sas

Stmicroelectronics France

Michael Soulie

Riccardo Locatelli

Giuseppe Guarnaccia

Raffaele Guarrasi

Giuseppe Maruccia

Valerio Catalano

Marcello Coppola

Loic Pallardy

Antonio-Marcello Coppola

Francesco Giotta

Thomas Martin

Hajer Ferjani

According to one aspect, provision is made of a system-on-chip comprising a master device, a slave device, a clock configured to clock the operation of the slave device, a clock controller configured to activate or deactivate the clock and/or a power-on controller configured to power on/off the slave device, a control system configured to detect that the clock is deactivated and/or that the slave device is powered off when the master device emits an access request to the slave device, the master device being configured for activating the clock when the control system detects that this clock is deactivated and/or powering on the slave device when the control system detects that the slave device is powered off, then emitting a new access request to the slave device.

System on a chip and a power down process for IP access resilience

The method for resetting a master device, configured to initiate transactions on a bus of a system on a chip, includes monitoring a completed or not state of the transactions initiated by the master device. In the case of reception of a command to reset the master device, the method includes a transmission of an effective reset command to the master device when the transactions initiated by the master device are in the completed state.

Method of resetting a master device of a system on chip and corresponding system on chip

A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.

Method and apparatus for supporting the use of interleaved memory regions

An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.

Method and apparatus for use with different memory maps

A method includes setting a first indicator to a first value, which causes an apparatus to stop receiving traffic from a traffic source. At least one register is accessed to read or write at least one new value, and a second indicator is set indicating that accessing of the at least one register has completed. The first indicator is set to a second value. When the first indicator has the second value and the second indicator is set, the apparatus is again allowed to receive traffic from the traffic source.

Method and apparatus for supporting reprogramming or reconfiguring

Embodiments relate to a method for transmitting a message in a data path of a network, the method includes transmitting a message onto an input bus of an input interface module, the message being received in flits of a size corresponding to the width of the input bus and generating a validity indicator for each elementary flit constituting each flit received. The message is transmitted onto an output bus of the input interface module towards a receiving interface module in flits of a size corresponding to the width of the output bus along with each validity indicator generated in association with the corresponding elementary flit. The receiving interface module receives flits constituting the message and the associated validity indicators and rejects a received flit if an elementary flit of the received flit is associated with a validity indicator in the invalid state.

Method of data transmission in a system on chip

A system is for transmitting data in a network and includes emitter nodes, each including a transmitter for transmitting requests for data transmission. The system may also include a receiver node receiving the data transmission from the emitter nodes and including a first memory for storing data transmitted by each emitter node, a second memory for storing the requests, and a transmitter. The data may be transmitted from the emitter nodes to the receiver node when memory space is available in the first memory to receive data. The transmitter of the receiver node may transmit to each emitter node an acknowledgement message when memory space is available in the first memory to receive at least a portion of the data transmitted. Each emitter node may establish a communication link with the receiver node and transmits the data based upon the acknowledgement message. The communication link may be locked until all data is transmitted.

Growing community of inventors

Voiron, France

Michael Soulie