Qualcomm Incorporated

Microsoft Technology Licensing, LLC

International Business Machines Corporation

Michael Scott McIlvaine

James Norris Dieffenderfer

Thomas Andrew Sartorius

Rodney Wayne Smith

Brian Stempel

Rami Mohammad Al Sheikh

Jeffrey Todd Bridges

Daren Eugene Streett

Thomas Philip Speier

Melinda Joyce Brown

Michael W Morrow

Kenneth Alan Dockser

Robert Douglas Clancy

Victor Roberts Augsburg

Saransh Jain

David Tennyson Harper, Iii

Gagan Gupta

Gregory Christopher Burda

Nathan Samuel Nunamaker

Leslie Mark DeBruyne

Jeffery Michael Schottmiller

Andrew S Irwin

Ahmed Helmi Mahmoud Osman Abulila

Raguram Damodaran

Yeshwant Nagaraj Kolla

Shivam Priyadarshi

Richard William Doing

Anil Krishna

Yusuf Cagatay Tekmen

Derek Robert Hower

Aaron Sebastian Giles

Rami Mohammad A Al Sheikh

Arthur Perais

Kiran Ravi Seth

Robert L Goldiez

Anthony Dale Klein

William James McAvoy

Vimal K Reddy

Les Mark DeBruyne

Sandeep Suresh Navada

Somasundaram Arunachalam

Niket Kumar Choudhary

Nathan Samuel Nunamker

Abdulhameed A Manadath

Spencer Williams

Serena Badran-Louca

Henry Arthur Pellerin, Iii

Jeffrey M Schottmiller

Kulin N Kothari

Kenneth Alan c/o Qualcomm Incorporated Dockser

Victor Robert Augsburg

Accelerating fetch target queue (FTQ) processing is disclosed herein. In some aspects, a processor comprises an FTQ and an FTQ acceleration cache (FAC), and is configured to generate a FAC entry corresponding to an FTQ entry of a plurality of FTQ entries of the FTQ, wherein the FTQ entry comprises a fetch address bundle comprising a plurality of sequential virtual addresses (VAs), and the FAC entry comprises metadata for the FTQ entry. The processor is further configured to receive, using the FTQ, a request to access the FTQ entry. The processor is also configured to, responsive to receiving the request to access the FTQ entry, locate, using the FAC, the FAC entry corresponding to the FTQ entry among a plurality of FAC entries of the FAC. The processor is additionally configured to perform accelerated processing of the request to access the FTQ entry using the metadata of the FAC entry.

Accelerating fetch target queue (FTQ) processing in a processor

Methods and circuitry for efficient management of local branch history registers are described. An example processor includes a pipeline comprising a plurality of stages and a bit-vector associated with each of in-flight branches associated with the pipeline. The processor includes a recovery counter for tracking a number of bits needing recovery before a local branch history register is valid for participation in branch prediction. The processor includes branch predictor circuitry configured to, in response to an update of a local branch history register by a branch, set a bit in a corresponding bit-vector indicative of the update of the local branch history register. The branch predictor circuitry is configured to, upon a flush, determine a value indicative of an extent of recovery required for each local branch history register affected by the flush, and set a corresponding recovery counter to the value indicative of the extent of recovery required.

Methods and circuitry for efficient management of local branch history registers

Selectively updating branch predictors for loops executed from loop buffers is disclosed herein. In some aspects, a branch predictor update circuit of a processor is configured to detect a loop comprising a plurality of loop instructions in an instruction stream, and to determine that the loop is stored within a loop buffer circuit of the processor. The branch predictor update circuit is further configured to determine a count of potential history register updates to the history register for the plurality of loop instructions, and to determine whether the count of potential history register updates exceeds a size of the history register. The branch predictor update circuit is also configured to, responsive to determining that the count of potential history register updates does not exceed the size of the history register, update a branch predictor of the branch predictor circuit based on the plurality of loop instructions.

Selectively updating branch predictors for loops executed from loop buffers in a processor

Providing extended branch target buffer (BTB) entries for storing trunk branch metadata and leaf branch metadata is disclosed herein. In one aspect, a processor comprises a BTB circuit comprising a BTB comprising a plurality of extended BTB entries. The BTB circuit is configured to store trunk branch metadata for a first branch instruction in an extended BTB entry of the plurality of extended BTB entries, wherein the extended BTB entry corresponds to a first aligned memory block containing an address of the first branch instruction. The BTB circuit is also configured to store leaf branch metadata for a second branch instruction in the extended BTB entry in association with the trunk branch metadata, wherein an address of the second branch instruction is subsequent to a target address of the first branch instruction within a second aligned memory block.

Providing extended branch target buffer (BTB) entries for storing trunk branch metadata and leaf branch metadata

Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions is disclosed. The processor is configured to support execution of read and/or write instructions that include obsolescence encoding indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. A register encoded as obsolescent means the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. Thus, such register can be set as being in an obsolescent state so that the data value stored in such register can be ignored to improve performance. As one example, data values for registers having an obsolescent state can be ignored and thus not stored in a saved context for a process being switched out, thus conserving memory and improving processing time for a process switch.

Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions

Performing branch predictor training using probabilistic counter updates in a processor is disclosed herein. In some aspects, a branch predictor training circuit of a processor is configured to determine whether a first branch prediction generated for a first conditional branch instruction by a branch predictor circuit of the processor is correct. Based on determining whether the first branch prediction is correct, the branch predictor training circuit probabilistically updates a first counter, corresponding to the first branch prediction, of a plurality of counters of a first branch predictor table of a plurality of branch predictor tables. In some aspects, the branch predictor training circuit probabilistically updates the first counter based on a global probability value corresponding to all branch predictor tables, while in some aspects the branch predictor training circuit is configured to probabilistically update the first counter based on a table-specific probability value corresponding to the first branch predictor table.

Performing branch predictor training using probabilistic counter updates in a processor

Delivering immediate values by using program counter (PC)-relative load instructions to fetch literal data in processor-based devices is disclosed. In this regard, a processing element (PE) of a processor-based device provides an execution pipeline circuit that comprises an instruction processing portion and a data access portion. Using a literal data access logic circuit, the PE detects a PC-relative load instruction within a fetch window that includes multiple fetched instructions. The PE determines that the PC-relative load instruction can be serviced using literal data that is available to the instruction processing portion of the execution pipeline circuit (e.g., located within the fetch window containing the PC-relative load instruction, or stored in a literal pool buffer), The PE then retrieves the literal data within the instruction processing portion of the execution pipeline circuit, and executes the PC-relative load instruction using the literal data.

Delivering immediate values by using program counter (PC)-relative load instructions to fetch literal data in processor-based devices

Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching is disclosed. An instruction processing circuit is configured to detect fetched performance degrading instructions (PDIs) in a pre-execution stage in an instruction pipeline that may cause a precise interrupt that would cause flushing of the instruction pipeline. In response to detecting a PDI in an instruction pipeline, the instruction processing circuit is configured to capture the fetched PDI and/or its successor, younger fetched instructions that are processed in the instruction pipeline behind the PDI, in a pipeline refill circuit. If a later execution of the PDI in the instruction pipeline causes a flush of the instruction pipeline, the instruction processing circuit can inject the fetched PDI and/or its younger instructions previously captured from the pipeline refill circuit into the instruction pipeline to be processed without such instructions being re-fetched.

Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching

A processor branch prediction circuit employs back-invalidation of prediction cache entries based on decoded branch instructions. The execution information of a previously executed branch instruction is obtained from a prediction cache entry and compared to generated decode information in an instruction decode circuit. Execution information of branch instructions stored in the prediction cache entry is updated in response to a mismatch of the execution information and the decode information of the branch instruction. Existing branch prediction circuits invalidate prediction cache entries of a block of instructions when the block of instructions is invalidated in an instruction cache. As a result, valid branch instruction execution information may be unnecessarily discarded. Updating prediction cache entries in response to a mismatch of the execution information and the decode information of the branch instruction maintains the execution information in the prediction cache.

Processor branch prediction circuit employing back-invalidation of prediction cache entries based on decoded branch instructions and related methods

Exemplary reach-based explicit dataflow processors and related computer-readable media and methods. The reach-based explicit dataflow processors are configured to support execution of producer instructions encoded with explicit naming of consumer instructions intended to consume the values produced by the producer instructions. The reach-based explicit dataflow processors are configured to make available produced values as inputs to explicitly named consumer instructions as a result of processing producer instructions. The reach-based explicit dataflow processors support execution of a producer instruction that explicitly names a consumer instruction based on using the producer instruction as a relative reference point from the producer instruction. This reach-based explicit naming architecture does not require instructions to be grouped in instruction blocks to support a fixed block reference point for explicit naming of consumer instructions, and thus is not limited to explicit naming of consumer instructions only within the same instruction block of the producer instruction.

Reach-based explicit dataflow processors, and related computer-readable media and methods

Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching is disclosed. An instruction processing circuit is configured to detect fetched performance degrading instructions (Pals) in a pre-execution stage in an instruction pipeline that may cause a precise interrupt that would cause flushing of the instruction pipeline. In response to detecting a PDI in an instruction pipeline, the instruction processing circuit is configured to capture the fetched PDI and/or its successor, younger fetched instructions that are processed in the instruction pipeline behind the PDI, in a pipeline refill circuit. If a later execution of the PDI in the instruction pipeline causes a flush of the instruction pipeline, the instruction processing circuit can inject the fetched PDI and/or its younger instructions previously captured from the pipeline refill circuit into the instruction pipeline to be processed without such instructions being re-fetched.

A cache management circuit that includes a predictive adjustment circuit configured to predictively generate cache control information based on a cache hit-miss indicator and the retention ranks of accessed cache lines to improve cache efficiency is disclosed. The predictive adjustment circuit stores the cache control information persistently, independent of whether the data remains in cache memory. The stored cache control information is indicative of prior cache access activity for data from a memory address, which is indicative of the data's 'usefulness.' Based on the cache control information, the predictive adjustment circuit controls generation of retention ranks for data in the cache lines when the data is inserted, accessed, and evicted. After the data has been evicted from the cache memory and is later accessed by a subsequent memory request, the persistently stored cache control information corresponding to that memory address increases the information available for determining the usefulness of data.

Cache management circuits for predictive adjustment of cache control policies based on persistent, history-based cache control information

Providing exception stack management using stack panic fault exceptions in processor-based devices is disclosed. In this regard, a processor device defines a 'stack panic fault exception' that may be raised upon execution of an exception handler store operation attempting to write state data into an exception stack, and provides a dedicated plurality of stack panic fault exception state registers in which stack panic fault exception state data may be saved. Upon detecting a first exception, the processor device transfers program control to an exception handler for the first exception. If a second exception occurs upon execution of a store operation in the exception handler, the processor device determines that the second exception should be handled as a stack panic fault exception, saves the stack panic fault exception state data in the stack panic fault exception state registers, and transfers program control to a stack panic fault exception handler.

Providing exception stack management using stack panic fault exceptions in processor-based devices

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Raleigh, NC, United States of America

Michael Scott McIlvaine