Lsi Corporation

Western Digital Corporation

Seagate Technology Incorporated

Other

Xiotech Corporation

Michael Scott Hicken

Timothy W Swatosh

Pamela Hempstead

Carl E Forhan

Martin S Dell

Timothy B Lund

Randy Reiter

Jackson L Ellis

Jeffrey L Williams

Steven M Howe

Vinay Ashok Somanache

Bryan Holty

James Edward Guttmann

Mark Ish

Earl Albert Cunningham

Leonid Baryudin

Alex G Tang

John Jeffrey Stephenson

Daniel John Sokolov

Mark David Heminger

Jonathan M Henze

Todd Barry Anderson

Clark A Anderson

Daniel D Reno

James N Snead

Gerald Lawrence Cadloni

John Paradise

Pamela S Hempstead

Systems and methods are disclosed for the intelligent scheduling of garbage collection operations on a solid state memory. In certain embodiments, a method may comprise initiating a garbage collection process for a solid state memory (SSM) having a multiple die architecture, determining an order of die access for the garbage collection process based on an activity table indicating a use of one or more die in the multiple die architecture, and performing the garbage collection process based on the determined order of die access. Garbage collection reads may be directed to idle die to avoid conflicts with die busy performing other operations, thereby improving system performance.

Garbage collection command scheduling

Apparatus and method for managing data in a hybrid data storage device. The device has a first non-volatile memory (NVM) of solid state memory cells arranged into a first set of garbage collection units (GCUs), and a second NVM as a rotatable data recording medium arranged into a second set of GCUs each comprising a plurality of shingled magnetic recording tracks. A control circuit combines a first group of logical block units (LBUs) stored in the first set of GCUs with a second group of LBUs stored in the second set of GCUs to form a combined group of LBUs arranged in sequential order by logical address. The control circuit streams the combined group of LBUs to a zone of shingled magnetic recording tracks in a selected one of the second set of GCUs. A combined media translation map identifies physical addresses in both the first and second NVMs.

Managing shingled magnetic recording (SMR) zones in a hybrid storage device

Described embodiments provide a media controller for a storage device having sectors, the sectors organized into blocks and superblocks. The media controller stores, on the storage device, logical-to-physical address translation data in N summary pages, where N corresponds to the number of superblocks of the storage device. A buffer layer module of the media controller initializes a summary page cache in a buffer. The summary page cache has space for M summary page entries, where M is less than or equal to N. For operations that access a summary page, the media controller searches the summary page cache for the summary page. If the summary page is stored in the summary page cache, the buffer layer module retrieves the summary page from the summary page cache. Otherwise, the buffer layer module retrieves the summary page from the storage device and stores the retrieved summary page to the summary page cache.

Accessing logical-to-physical address translation data for solid state disks

A method for handling meta data stored in a page of a flash memory within a flash media controller. The method generally includes (i) defining the meta data on a per context basis, where the context is defined on a per page basis, (ii) when a size of the meta data is less than or equal to a predefined threshold, storing the complete meta data within a structure of the context, and (iii) when the size of the meta data is greater than the predefined threshold, defining meta data pointers within the context.

Meta data handling within a flash media controller

A method of controlling a flash media system. The method includes providing a flash lane controller having a processor control mode and creating and presenting soft contexts. The soft contexts generally place the flash lane controller into the processor control mode. In the processor control mode, the flash lane controller stores the entire soft context, finishes executing any outstanding contexts, suspends normal hardware automation, and then executes the soft context.

Flexible flash commands

A flash-memory system is organized into a plurality of blocks and a plurality of pages in each block, each page having 2data locations and K spare locations. At least one page in the memory has 2user data sectors and each sector has 2+L locations therein. Because L is at least 1 but less than 2, user data is stored in the spare memory locations. By storing user data in spare locations that were previously off-limits to user data, enterprise-sized sectors can be efficiently stored in flash memories with little wasted memory, thereby making flash-memory systems compatible with existing hard-drive storage systems in enterprise system applications.

Flash memory organization

Described embodiments provide a host subsystem that generates a host context corresponding to a received host data transfer request. A programmable sequencer generates one or more sequencer contexts based on the host context. Each of the sequencer contexts corresponds to at least part of the host data transfer request. The sequencer contexts are provided to a buffer subsystem of the media controller. For host read requests, the buffer subsystem retrieves the data associated with the sequencer contexts of the read request from a corresponding buffer or a storage media and transmits the data associated with the sequencer contexts to the host device. For host write requests, the buffer subsystem receives the data associated with the host context from the host device and stores the data associated with the sequencer contexts of the write request to a corresponding buffer or the storage media.

Processing host transfer requests for direct block access storage devices

Described embodiments provide a media controller that synchronizes data cached in a buffer and corresponding data stored in one or more sectors of a storage device. A buffer layer module of the media controller caches data transferred between the buffer and the storage device. One or more contiguous sectors are associated with one or more chunks. The buffer layer module updates a status corresponding to each chunk of the cached data and scans the status corresponding to a first chunk of cached data. If, based on the status, the first chunk of cached data is more recent than the corresponding data stored on the storage device, a media layer module synchronizes the data on the storage device with the cached data. The status corresponding to the group of one or more sectors is updated. The media layer module scans a next chunk of cached data, if present.

Cache synchronization for solid state disks

Described embodiments provide a method of transferring, by a media controller, data associated with a host data transfer between a host device and a storage media. A buffer layer module of the media controller segments the host data transfer into one or more data transfer segments. Each data transfer segment corresponds to at least a portion of the data. The buffer layer module allocates a number of physical buffers to a virtual circular buffer for buffering the one or more data transfer segments. The buffer layer module transfers, by the virtual circular buffer, each of the data transfer segments between the host device and the storage media through the allocated physical buffers.

Buffering of data transfers for direct access block devices

Described embodiments provide reconstruction of logical-to-physical address mapping data for one or more sectors of a storage device at startup of a media controller. The sectors of the storage device are organized into blocks and superblocks and the address mapping data is stored in a volatile memory. At a startup condition of the media controller, a buffer layer module of the media controller allocates space in the volatile memory for one or more logical-to-physical address mapping data structures. A media layer module of the media controller determines a block type of each block of the storage device and places each block of the storage device into corresponding groups based on the determined block type of each block. The one or more blocks of each group are processed, and one or more address mapping data structures for the storage device are constructed in the allocated space in the volatile memory.

Startup reconstruction of logical-to-physical address translation data for solid state disks

A flash-memory system is organized into a plurality of blocks and a plurality of pages in each block, each page having 2data locations and K spare locations. At least one page in the memory has 2&#x2212;1 user data sectors and each sector has 2+L locations therein. Error-correction code (ECC) data related to the user data is calculated and stored in at least the 2user data locations unused by the 2&#x2212;1 user data sectors. Because L is at least 1 but less than 2(N&#x3e;M), at least a portion of one user data sector is stored in the spare memory locations. Additional locations in each page are available to allow for the ECC data to have additional redundancy bits added per sector, thereby making the flash memory system more robust and reliable.

Described embodiments provide logical-to-physical address translation for data stored on a storage device having sectors organized into blocks and superblocks. A flash translation layer maps a physical address in the storage device to a logical sector address. The logical sector address corresponds to mapping data that includes i) a page index, ii) a block index, and iii) a superblock number. The mapping data is stored in at least one summary page corresponding to the superblock containing the physical address. A block index and a page index of a next empty page in the superblock are stored in a page global directory corresponding to the superblock. A block index and a page index of the at least one summary page and the at least one active block table for each superblock are stored in at least one active block table of the storage device.

Logical-to-physical address translation for solid state disks

Described embodiments provide skip operations for transferring data to or from a plurality of non-contiguous sectors of a solid-state memory. A host layer module sends data to, and receives commands from, a communication link. Received commands are one of read requests or write requests, with commands including i) a starting sector address, ii) a skip mask indicating the span of all sector addresses in the request and the sectors to be transferred, iii) a total number of sectors to be transferred; and, for write requests, iv) the data to be written to the sectors. A buffer stores data for transfer to or from the solid-state memory. A buffer layer module i) manages the buffer, ii) segments the span of the request into a plurality of chunks, and iii) determines, based on the skip mask, a number of chunks to be transferred to or from the solid-state memory.

Skip operations for solid state disks

A method, apparatus, and system for preserving the cache data of redundant storage controllers, by copying the recorded data blocks and the associated cache tags in the primary cache memory of a storage controller to a secondary cache memory of an alternate, redundant storage controller, wherein upon a failure occurring in the primary cache memory of any of the storage controllers, subsequent storage requests from a host, previously intended for processing by the failed storage controller, are processed through the secondary cache memory of a non-failed, redundant storage controller that contains the failed storage's controller cache data and cache tags.

Method, apparatus, and system for preserving cache data of redundant storage controllers

In a ultra high density, multiple-disk drive, track switches within a cylinder of tracks as well as track switches to tracks on other cylinders both require a movement of the head stack actuator. Track switching latency in such a disk drive is reduced by overlapping pre-movement portions of the track switching process with the data transfer operation of the currently active recording head. In addition, post-movement portions of the track switching process are overlapped with the movement of the heads so that the next selected read/write head may begin a data transfer operation immediately upon arrival at the next track. Further, the pre-movement and post-movement portions of the track-switch process may be overlapped with low displacement movement of the read/write heads relative to the currently active track or the next track.

Growing community of inventors

Rochester, MN, United States of America

Michael Scott Hicken