Agere Systems Inc.

Lucent Technologies Inc.

Agere Systems Guardian Corp.

Michael Scott Carroll

Tony G Ivanov

Daniel Charles Kerr

Amal Ma Hamad

Roger W Key

Thiet The Lai

Samir Chaudhry

Alan Sangone Chen

Yih-Feng Chyan

Samuel Suresh Martin

Yi Ma

Kuo-Hua Lee

Ranbir Singh

Edward Belden Harris

Sylvia Thomas

Richard William Gregor

Frank Yauchee Hui

Minesh Amrat Patel

William John Nagy

Robert W Dail

Peyman Sana

Michael Jay Parrish

A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed.

Multiple doping level bipolar junctions transistors and method for forming

Method for forming multiple doping level bipolar junctions transistors

A low-thermal budget, silicon-rich silicon nitride film may include a concentration of hydrogen in Si&#x2014;H bonds being at least 1.5 times as great as a concentration of hydrogen in N&#x2014;H bonds. The silicon nitride film suppresses boron diffusion in boron-doped devices when such devices are processed using high-temperature processing operations that conventionally urge boron diffusion. The low-thermal budget, silicon-rich silicon nitride film may be used to form spacers in CMOS devices, it may be used as part of a dielectric stack to prevent shorting in tightly packed SRAM arrays, and it may be used in BiCMOS processing to form a base nitride layer and/or nitride spacers isolating the base from the emitter. Furthermore the low-thermal budget, silicon-rich silicon nitride film may remain covering the CMOS structure while bipolar devices are being formed, as it suppresses the boron diffusion that results in boron penetration and boron-doped poly depletion.

Silicon-rich low thermal budget silicon nitride for integrated circuits

A semiconductor device having a capacitor integrated in a damascene structure. In one embodiment, the capacitor is formed entirely within a metallization layer of a damascene structure, having therein a semiconductor device component. Preferably, the capacitor is formed within a trench, having been etched in the dielectric material of the metal layer and the capacitor includes a first capacitor electrode formed within the recess in electrical contact with the device component of the metallization layer. An insulator may be formed over the first capacitor electrode, with a second capacitor electrode formed over the insulator. These elements are preferably conformally deposited within the trench, thereby forming a recess, a portion of which extends within the trench. A subsequently fabricated device component may then be placed in electrical contact with the second capacitor electrode.

Capacitor for a semiconductor device and method for fabrication therefor

A method for electromagnetically shielding circuits which combine to form an integrated circuit device provides isolated silicon islands surrounded laterally and subjacently by conductive material. The isolated silicon islands may be covered individually or as a group by a conductive cover. The integrated circuit may include at least one silicon island including an analog circuit and at least one silicon island including a digital circuit, the analog and digital circuits electromagnetically shielded from one another. The method for forming the structure includes providing a first semiconductor substrate and hydrophilically bonding a substructure to the first semiconductor substrate. The substructure includes the isolated silicon islands surrounded by the conductive material. The substructure may be formed on a second semiconductor substrate by implanting an impurity region into an upper portion of the second semiconductor substrate. After bonding, the substructure may be separated from the remainder of the second substrate by propagating a crack along the boundary of the impurity region which separates the substructure from the remainder of the second semiconductor substrate. The method further includes forming the conductive cover over the isolated silicon island or islands by forming insulating layers over the silicon islands then forming a conductive cover layer and conductive sidewalls to surround the silicon island or islands being enclosed.

Method and structure for DC and RF shielding of integrated circuits

A bipolar vertical PNP transistor compatible with CMOS processing and useful in a complementary BiMOS structure is characterized in that it is devoid of an epitaxial layer and employs a high-energy implanted phosphorus layer to provide N-type substrate isolation.

Vertical PNP bipolar transistor and its method of fabrication

A resistor fuse for use in a semiconductor device having an operating voltage. In one embodiment, the resistor fuse includes a silicon layer located over a semiconductor wafer and a metal silicide layer located over the silicon layer. The resistor fuse has a predetermined current threshold and is configured to open if a current through the resistor fuse at the operating voltage exceeds the current threshold.

Resistor fuse

Article for de-embedding parasitics in integrated circuits

A wafer configured for in-process testing of electrical components has a plurality of dies disposed on the wafer, wherein adjacent dies are separated from one another by streets. An in-line device monitor having a first port, a second port, and a device-under-test substantially in line with one another is placed within a street, where the device-under-test is between the first and second ports and is electrically coupled to the first and second ports. With such an arrangement, streets having a width of 100 microns and less are suitable for accomodating a RF-device monitor having ground-signal or ground-signal-ground configurations. As a result, accurate GS or GSG RF-device monitors can be provided in narrow streets of wafers, thereby increasing the amount of wafer area available for circuitry.

Inline ground-signal-ground (GSG) RF tester

Integrated circuit comprising means for high frequency signal transmission

A bipolar fabrication process, illustratively suited for integration into a conventional CMOS process to thereby form a BiCMOS integrated circuits is disclosed. The collector and base are formed through multiple implants and a single masking step to thereby provide a continuous low resistance collector region.

Process for making bipolar having graded or modulated collector

Growing community of inventors

Orlando, FL, United States of America

Michael Scott Carroll