Sk Hynix Nand Product Solutions Corp.

Skhynix Inc.

Intel Corporation

Michael Scott Allison

Shirish Dnyaneshware Bahirat

Joseph Tarango

Eric Hoffman

Randal Eike

Mary Allison Goodman

John Rudelic

David J Pignatelli

Johnny A Lam

Mary Goodman

MadhuKiran Vaddi

A method is described. The method includes executing solid state drive program code from system memory of a computing system to perform any/all of garbage collection, wear leveling and logical block address to physical block address translation routines for a solid state drive that is coupled to a computing system that the system memory is a component of.

Solid state drive with external software execution to effect internal solid-state drive operations

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to two or more persistent storage devices, wherein at least one of the two or more persistent storage devices is to be logically organized with a namespace divided into two or more zones, determine two or more different zone size dependent parameters associated with the two or more persistent storage devices, determine a smallest aligned boundary based on each of the two or more different zone size dependent parameters, and set a zone group size for access to the two or more persistent storage devices based on the determined smallest aligned boundary. Other embodiments are disclosed and claimed.

Zoned namespace with zone grouping

An embodiment of a semiconductor apparatus may include technology to provide placement option information to a host in response to a host query, and create a namespace to access a persistent storage media based on host-provided isolation granularity information. Other embodiments are disclosed and claimed.

Host defined bandwidth allocation for SSD tasks

A system and an operating method thereof include a system on chip (SOC) flash controller having at least one SOC channel; at least one memory device coupled with the at least one SOC channel; a printed circuit board (PCB), wherein the SOC flash controller and the at least one memory device are mounted thereon; a flash address translation (FTL) address translator automatically managing the at least one memory device in accordance with a PCB board configuration file of the PCB board and a drive configuration file of the at least one memory device; and a fuse storing an open data plane (ODP) fuse setting generated in accordance with at least in part with data of the PCB board configuration file and the drive configuration file.

System of multiple configurations and operating method thereof

A memory system includes a plurality of memory channels, each of the plurality of memory channels includes a plurality of memory dies and a die processor, each of the plurality of memory dies includes a plurality of memory blocks; and a memory controller including a monarch processor, coupled to the plurality of memory channels, wherein the die processor on each of the plurality of memory channels is configured in parallel to process to find last written data within at least a predetermined block of the plurality of memory dies; and provide information regarding the last written data to the monarch processor, the monarch processor determines which boot record to be used to identify firmware images based on the information.

Growing community of inventors

Longmont, CO, United States of America

Michael Scott Allison