Infineon Technologies Ag

Michael Schrenk

Manfred Engelhardt

Uwe Seidel

Hubert Werthmann

Guenther Schindler

Markus Schwerd

Wolfgang Walter

Heinrich Körner

Rudolf Lachner

Christian Herzum

Alexander Gschwandtner

Jürgen Holz

Klaus Koller

Gabriele Bettineschi

Andreas Stich

A semiconductor device comprises a semiconductor substrate, an anorganic isolation layer on the semiconductor substrate and a metallization layer on the anorganic isolation layer. The metallization layer comprises a fuse structure. At least in an area of the fuse structure the metallization layer and the anorganic isolation layer have a common interface.

Semiconductor device comprising a fuse structure and a method for manufacturing such semiconductor device

An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which is formed on the surface of the exposed first capacitor electrode. On the diffusion barrier layer and on the side walls of the opening there is also formed a capacitor dielectric and a second capacitor electrode on top.

MIM capacitor and associated production method

The invention relates to an overvoltage protection apparatus having a semiconductor substrate, a first doping region in order to provide a protection diode, and a second doping region in order to provide a protection resistance, with the second doping region being immediately adjacent to the first doping region.

Overvoltage protection apparatus and an associated protection circuit

A capacitor assembly has a substrate, a first conductive auxiliary layer on the substrate, a capacitor dielectric, a second conductive auxiliary layer and a contact electrode. Thereby the first conductive auxiliary layer is connected to the capacitor dielectric within a first boundary area and the second conductive auxiliary layer is connected to the capacitor dielectric within a second boundary area. Thereby, an effective capacitor area is present where the first boundary area and the second boundary area overlap across the capacitor dielectric. The contact electrode is connected to the first conductive auxiliary layer in a contacting area, wherein the contacting area is disposed on a surface of the first conductive auxiliary layer opposite to the first boundary area and overlaps the effective capacitor area partly or not at all, so that at least part of the first conductive auxiliary layer within the effective capacitor area is adjacent to the substrate or not to the contact electrode.

Capacitor assembly having a contact electrode encircling or enclosing in rectangular shape an effective capacitor area

To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric auxiliary layer () is deposited on a first electrode (). This auxiliary layer () is then opened up () via the first electrode. Then, a dielectric layer () is produced, and the metal track stack () for the second electrode is then applied to the dielectric layer (). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.

Integrated semiconductor product with metal-insulator-metal capacitor

To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric protective layer () and a dielectric auxiliary layer () are deposited on a first electrode (). The protective layer and the auxiliary layer () are then opened up () via the first electrode. Then, a dielectric layer () is produced, and the metal track stack () for the second electrode is then applied to the dielectric layer (). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.

Integrated semiconductor product comprising a metal-insulator-metal capacitor

A capacitor stack in a layer structure of an integrated component has the same layer sequence as an adjacent interconnect, with the exception of a dielectric interlayer. This significantly facilitates the fabrication of vias.

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Diessen am Ammersee, Germany

Michael Schrenk