Intel Corporation

Michael S Yang

Avinash Sodani

Aditya Kesiraju

Roger Gramunt

Benjamin C Chaffin

Ramon Matas

Alexey Suprun

Julio Gago

Chung-Lun Chan

Rammohan Padmanabhan

Neal S Moyer

Vikram S Sundaram

Gerardo A Fernandez

In one embodiment, a processor includes a frontend unit having an instruction decoder to receive and to decode instructions of a plurality of threads, an execution unit coupled to the instruction decoder to receive and execute the decoded instructions, and an instruction retirement unit having a retirement logic to receive the instructions from the execution unit and to retire the instructions associated with one or more of the threads that have an instruction or an event pending to be retired. The instruction retirement unit includes a thread arbitration logic to select one of the threads at a time and to dispatch the selected thread to the retirement logic for retirement processing.

Scalable event handling in multi-threaded processor cores

Growing community of inventors

Hillsboro, OR, United States of America

Michael S Yang