Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Hewlett Packard Enterprise Development LP

Samsung Electronics Co., Ltd.

Institute for the Development of Emerging Architectures, L.l.c.

Idea Corporation

Hewlett Packard Enterprise Department LP

Michael S Schlansker

Vinod Kumar Kathail

Jean Tourrilhes

Boon Seong Ang

Rajiv Gupta

Shail Aditya Gupta

Michael Renne Ty Tan

Yoshio Frank Turner

Shih-Yuan Wang

Norman Paul Jouppi

Philip John Kuekes

Robert S Schreiber

Dale Calvin Morris

Tse-Yu Yeh

Paul Allen Bottorff

Boon Yong Ang

Wayne V Sorin

Millind Mittal

Puneet Sharma

Terrel L Morris

Alan Hersh Karp

Jeffrey Clifford Mogul

Sujata Banerjee

Moray McLaren

Nathan Lorenzo Binkert

Harshvardhan P Sharangpani

Santosh Abraham

Jung Gun Lee

Rajendra Kumar

Priya Mahadevan

Michael Paul Corwin

Dwight L Barron

Praveen Yalagandula

B Ramakrishna Rau

Erwin Oertli

Jean-Francois C Collard

Jose Renato G Santos

Frederic C Amerson

William S Worley, Jr

Stephen G Low

Bantwal R Rau

Mircea Poplingher

Kent G Fielden

Richard C Johnson

Jean-Francois C P Collard

Hans J Mulder

Jayaram Mudigonda

Charles L Hudson

Mukund Sivaraman

Charles B Morrey, Iii

Guodong Zhang

Milind M Chabbi

Darren Charles Cronquist

Norm Jouppi

Scott A Mahlke

Lucian Popa

Joseph A Fisher

Alvin Auyoung

Balasubramanian Kumar

Christian Bell

Anita B Rau

Darren C Conquist

Greg Snider

Jean Tourrihes

Adarsh Yoga

Bantwai R Rau

Jean Tourrilhs

Examples disclosed herein relate to path-synchronous performance monitoring of an interconnection network based on source code attribution. A processing node in the interconnection network has a profiler module to select a network transaction to be monitored, determine a source code attribution associated with the network transaction to be monitored, and issue a network command to execute the network transaction to be monitored. A logger module creates, in a buffer, a node temporal log associated with the network transaction and the network command. A drainer module periodically captures the node temporal log. The processing node has a network interface controller to receive the network command and mark a packet generated for the network command to be temporally tracked and attributed back to the source code attribution at each hop of the interconnection network traversed by the marked packet.

Path-synchronous performance monitoring of interconnection networks based on source code attribution

Examples disclosed herein relate to partial cache coherence. In some examples disclosed herein, a node connected to a memory fabric may include local cache connected to a local processor and a memory coherency proxy to. The memory coherency proxy may configure a portion of a fabric memory on the memory fabric as a proxy backing memory and expose the proxy backing memory to other nodes in the memory fabric as a fictitious local memory on the node, and may implement partial coherency for memory requests directed to the fictitious local memory. The fictitious local memory may have a memory address region different from a memory address region of a native local memory on the node.

Partial cache coherence

Examples disclosed herein relate to locally polling the value of a flag to determine whether a resource is free for a thread to use in a system with multiple processing nodes that are incoherent with regards to each other. A flag in a direct attached memory to one of the processing nodes is set to indicate that the resource is not free for the thread to use. A previous tail of a lock list is determined from a list master. The previous tail is located on another one of the processing nodes.

Locally poll flag in multi processing node system to determine whether a resource is free to use for thread

An example method for allocating resources in accordance with aspects of the present disclosure includes collecting proposals from a plurality of modules, the proposals assigning the resources to the plurality of modules and resulting in topology changes in a computer network environment, identifying a set of proposals in the proposals, the set of proposals complying with policies associated with the plurality of modules, instructing the plurality of modules to evaluate the set of proposals, selecting a proposal from the set of proposals, and instructing at least one module associated with the selected proposal to instantiate the selected proposal.

Resource allocator

A technique includes using circuit switches to selectively couple packet switches of a switch assembly to the port connectors of the assembly.

Switch assembly

Embodiments herein relate to addition or modification to a forwarding table based on an address. A first packet having a source address and a location value may be received. The source address includes a source of the first packet and the location value indicates at least part of a route along a network to the source address. The forwarding table is not modified or no new entry is added to the forwarding table, if the forwarding table does not include the source address.

Modification or addition to forwarding table based on address

One example provides a network device including a queue to receive frames from a source, a processor, and a memory communicatively coupled to the processor. The memory stores instructions causing the processor, after execution of the instructions by the processor, to determine whether a flow control threshold of the queue has been exceeded, and in response to determining that the flow control threshold of the queue has been exceeded, generate a message to be sent to the source of the frame that exceeded the flow control threshold. The message includes a pause duration for which the source is to stop transmitting frames.

Flow control in a network

A configurable Clos network includes leafs and spines and a switch fabric that connects the leafs and the spines. The switch fabric couples each leaf port of each leaf to at least one spine port of each spine.

Configurable Clos network

An optical interconnect () includes: a reflective body () having a first reflective surface () and a second reflective surface () opposite the first reflective surface (); a first optical waveguide () that directs a first optical signal received from a first communicating device () to the first reflective surface (); a second optical waveguide () that directs the first optical signal from the first reflective surface () of the reflective body () to a second communicating device (); a third optical waveguide () that directs a second optical signal received from the second communicating device () to the second reflective surface () of the reflective body (); and a fourth optical waveguide () that directs the second optical signal from the second reflective surface () of the reflective body () to the first communicating device ().

Optical interconnect

A method for load balancing Ethernet traffic within a fat tree network () includes randomly assigning incoming messages () into hash classes using a hash function (); allocating the hash classes among uplinks (); and transmitting the incoming messages on the uplinks () according to the hash class. A network switch () for load balancing communication flows in a fat tree network () includes downlinks () and uplinks (); the network switch () being configured to route communication flows among the downlinks () and uplinks (); a hash module () which receives a MAC address from a message () and outputs a hash address; and a TCAM lookup module () which allocates the hash address into a hash class and allocates the hash class to one of the uplinks ().

Load balancing

Systems, methods, and apparatus to route optical signals are disclosed. An example apparatus to route optical signals includes a plurality of hollow metal waveguide optical switch arrays. Each of the arrays comprises a plurality of optical input ports and a plurality of optical output ports. The input ports and the output ports for a first one of the arrays are arranged in a first plane, the input ports and the output ports for a second one of the arrays are arranged in a second plane, and the plurality of arrays are stacked such that the first and second planes are adjacent. The first one of the arrays is to convey optical signals from a first communication device to a second communication device and the second one of the arrays is to convey optical signals from the second communication device to the first communication device.

Routing optical signals

Systems and methods for providing network interface controllers (NICs) with memory-mapped buffers are described. A processing system includes a plurality of processing cells, each including at least one processor and at least one system memory. A NIC is associated with each of the processing cells for transmitting and receiving data between the processing cells. Each of the cells further includes a memory interconnect to which the NIC is directly connected and the NIC includes at least one memory-mapped buffer.

Memory-mapped buffers for network interface controllers

In a method () for routing packets between a plurality of top switches (-) and a plurality of leaf switches (-) using a balancing table () in a fat tree network (), a failed link between at least one top switch () and at least one leaf switch () is detected (). In addition, the balancing table () is modified () based on the detected failed link, and the packets are routed () between the plurality of top switches (-) and the plurality of leaf switches (-) in the fat tree network () based on the modified balancing table ().

Method for routing data packets in a fat tree network

A system and method are provided to route packets in a data center network. Individual packets are encapsulated at an edge of the data center network, so that each encapsulated packet includes a set of header fields, such as a tenant identifier. For each encapsulated packet, a hash class is determined from the set of header fields. A routing virtual local area network (VLAN) is selected for the packet based on the tenant identifier and the hash class.

Routing encapsulated data packets onto selected VLANs

A computer system is provided including a central processing unit having an internal cache, a memory controller is coupled to the central processing unit, and a closely coupled peripheral is coupled to the central processing unit. A coherent interconnection may exist between the internal cache and both the memory controller and the closely coupled peripheral, wherein the coherent interconnection is a bus.

Computer system with coherent interconnection

Growing community of inventors

Los Altos, CA, United States of America

Michael S Schlansker