Microchip Technology Inc.

Michael S Pyska

Joseph W Triece

Igor Wojewoda

Michael I Catherwood

James B Nolan

Ryan Scott Ellison

Cristian P Masgras

Joshua M Conner

Edward Brian Boles

Mei-Ling Chen

A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.

Enabling special modes within a digital device

A processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.

Dynamically reconfigurable data space

An oscillator with temperature compensation produces a stable clock frequency over wide variations of ambient temperature, and it includes an oscillation generator, two independent current generators, a transition detector and a clock inhibitor. The outputs of the two programmable, independent current generators are combined to provide a capacitor charging current that is independent of temperature. The oscillator is capable of three modes of operation: fast mode, slow/low power mode and sleep mode, which are controlled by the transition detector in response to external control signals. When the transition detector transitions from one mode to another, it controls the clock inhibitor to block a clock output of the oscillator generator for a predetermined number of clock cycles to allow the clock output to stabilize. The oscillator is implemented on a single, monolithic integrated circuit.

Oscillator with clock output inhibition control

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Phoenix, AZ, United States of America

Michael S Pyska