Virginia Tech Intellectual Properties, Inc.

Fujitsu Corporation

Syntest Technologies, Inc.

Michael S Hsiao

Jawahar Jain

Mukul Ranjan Prasad

Laung-Terng Wang

Shianling Wu

Zhigang Jiang

Nur A Touba

Kameshwar Chandrasekar

Disclosed are various embodiments for automated program synthesis from a natural language for domain specific computing applications. In one embodiment, a natural language processor may be configured to parse words from a sentence of text formed in a natural language, such as English, following a grammatical structure for the natural language. The words may be compared to a dictionary to identify a token. The text formed in the natural language may be converted to an intermediate format of programming code in a programming language, such as C, where the intermediate format includes the token. The token may invoke a function or a routine of a library written in the programming language. The intermediate format may be compiled into executable program code to generate an application, such as a video game, for execution.

Automated program synthesis from natural language for domain specific computing applications

A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss.

Method and apparatus for testing 3D integrated circuits

An all solutions automatic test pattern generation (ATPG) engine method uses a decision selection heuristic that makes use of the 'connectivity of gates' in the circuit in order to obtain a compact solution-set. The 'symmetry in search-states' is analyzed using a &#x201c;Success-Driven Learning&#x201d; technique which is extended to prune conflict sub-spaces. A metric is used to determine the use of learnt information a priori, which information is stored and used efficiently during &#x201c;success driven learning&#x201d;.

Decision selection and associated learning for computing all solutions in automatic test pattern generation (ATPG) and satisfiability

Generating a test sequence includes receiving a circuit representation describing a circuit, and a fault associated with the circuit representation. A miter circuit model associated with a good circuit model and a faulty circuit model is established according to the circuit representation. A satisfiability problem corresponding to the fault as associated with the miter circuit model is also established. Whether the satisfiability problem is satisfiable is determined. If the satisfiability problem is satisfiable, a test sequence is generated for the fault as associated with the miter circuit model.

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Blacksburg, VA, United States of America

Michael S Hsiao