Micron Technology Incorporated

Michael S Cohen

James M Shaffer

Karl H Mauritz

Glen G Atkins

Thomas W Voshell

Charles W Tillinghast

An apparatus for integrating wafer scale semiconductor integrated circuits and interfacing them with other systems. A wafer, partial wafer, die or plurality of same are mated to a printed circuit board (PCB) which electrically contacts the pads on each die using small conductive pillars. The PCB in turn is connected easily to other electronic systems. The entire apparatus is incorporated into other systems which utilize the dice in the apparatus. The apparatus may be fitted with heating elements and cooling channels to generate the necessary die temperatures for burn-in, testing, and operation. The apparatus is easily adaptable to include more dice in a stacked configuration.

Repairable wafer scale integration system

A method of forming electrically conductive pillars on a printed circuit board by providing a printed circuit board having a plurality of electrical traces and forming a plurality of elongate, electrically conductive pillars of superimposed layers of solder and conductive polymer on the printed circuit board. The elongate, electrically conductive pillars are connected by a first end to the electrical traces of the printed circuit board and extend substantially perpendicularly from the printed circuit board such that a second end of each of the plurality of elongate, electrically conductive pillars lies in substantially a common plane which is substantially perpendicular to and above said printed circuit board.

Method of forming electrically conductive pillars

An apparatus for wafer scale burn-in and testing of semiconductor integrated circuits and a method for its utilization is disclosed. A wafer is mated to a printed circuit board which electrically contacts the pads on each die using small conductive pillars. Single precise alignment of entire wafer within apparatus allows for testing all the dice on the wafer in parallel, eliminating need to probe each die individually. The apparatus is fitted with heating elements and cooling channels to generate the necessary wafer temperatures for burn-in and testing. The method of utilization eliminates processing of defective dice beyond burn-in and test, thereby increasing throughput.

Wafer scale burn-in apparatus and process

An apparatus for integrating wafer scale semiconductor integrated circuits and interfacing them with other systems. A wafer, partial wafer, die or plurality of same are mated to a printed circuit board (PCB) which electrically contacts the pads on each die using small conductive pillars. The PCB in turn is connected easily to other electronic systems. The entire apparatus is incorporated into other systems which utilize the dice in the apparatus. The apparatus may be fitted with heating elements and cooling channels to generate the necessary dice temperatures for burn-in, testing, and operation. The apparatus is easily adaptable to include more dice in a stacked configuration.

An apparatus for wafer scale burn-in and testing of semiconductor integrated circuits and a method for its utilization. A wafer is mated to a printed circuit board which electrically contacts the pads on each die using small conductive pillars. Single precise alignment of entire wafer within apparatus allows for testing all the dice on the wafer in parallel, eliminating need to probe each die individually. The apparatus is fitted with heating elements and cooling channels to generate the necessary wafer temperatures for burn-in and testing. The method of utilization eliminates processing of defective dice beyond burn-in and test, thereby increasing throughput.

A temperature sensing circuit allows a DRAM array to use less power than would normally be possible due to the reduced refresh rate based on the temperature of the DRAM array. The temperature circuit removes the refresh guardbanding on the DRAMS. Instead of refreshing a 1 megabyte DRAM every 8 ms, refreshing the DRAMs every 128 ms is possible, depending on the temperature of the DRAM array.

Temperature-dependent DRAM refresh circuit

A dynamic random access memory (DRAM) array is configured to appear to a host computer as a static random access memory (SRAM) array. This allows the use of a component which is functionally equivalent to an SRAM array, but which is less costly and which provides more memory in the same unit area. A temperature sensing circuit allows the DRAM array to use less power than would normally be possible by using a reduced refresh rate based on the temperature of the DRAM array. For example, instead of refreshing a 1 megabyte DRAM every 8 ms, refreshing the DRAM every 128 ms is possible, depending on the temperature of the DRAM array.

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Boise, ID, United States of America

Michael S Cohen