Advanced Micro Devices Corporation

Fujitsu Corporation

Other

Michael S Chung

Pau-Ling Chen

Binh Quang Le

Shane Charles Hollmer

Masaru Yano

Vincent C Leung

Shoichi Kawamura

James Jiahua Yu

Michael Van Buskirk

Keith H Wong

A method of reading a memory cell, and a memory array using the method, are described. An electrical load is applied to a first node in the memory array, the first node corresponding to the memory cell. A second node in the memory array, the second node on a same word line as the first node, is precharged. The second node is separated from the first node by at least one intervening node in the same word line.

Precharging scheme for reading a memory cell

A flash memory array having multiple dual bit memory cells divided into section attached to a wordline and a pair of reference cells logically associated with each section. A method of reprogramming a section or sections of words that are required to be changed includes inputting allowed changes to the flash memory array, reading word or words to be changed in each section, programming bits in word or words to be changed in each section, refreshing previously programmed bits in the word or words that are changed, refreshing previously programmed bits in the word or words changed in each section, refreshing previously programmed bits in the remaining word or words in each section and refreshing previously programmed in each pair of reference cells in the section in which changes have been made.

Refresh scheme for dynamic page programming

A method is provided for selecting a group of memory blocks in a flash memory device given their starting and ending addresses. The method compares the two addresses to determine the multi-block first bit location which is the most significant bit location where the starting and ending addresses have different bits. The method then generates a converted memory block address where bits more significant than the multi-block first bit location are the ending address bits and where bits less significant than, or equal in significance to, the multi-block first bit location are equal to a logic 1. The method also generates a converted complementary memory block address identical to the other converted address except that bits in the bit locations more significant than the multi-block first bit location are the complements of the ending address bits. The method then pre-decodes the two converted addresses to generate sets of pre-decoded z-signals corresponding to the block addresses included in a group of the starting and ending addresses and all the addresses between them. Finally, the method decodes the pre-decoded z-signals to generate signals selecting memory blocks whose addresses are in that group.

Multi-set block erase

The present invention is a power-on reset circuit that generates a precise power-on reset pulse with an upper threshold voltage that is highly insensitive to variations in temperature and integrated circuit fabrication processes. The power-on reset circuit of the present invention includes a self-biased current generator capable of receiving a supply voltage and generating a first current, which is proportional to an absolute temperature, in response to receiving the supply voltage. The power-on reset circuit of the present invention also includes a base-emitter voltage detector that is coupled to the self-biased current generator such that a second current flowing though the base-emitter voltage detector is substantially equal to the first current generated by the self-biased current generator. Furthermore, the power-on reset circuit of the present invention includes a (BiCMOS) inverter that is coupled to the base-emitter voltage detector such that the BiCMOS inverter generates the power-on reset pulse as the supply voltage is turned on. With such a power-on reset circuit of the present invention, the upper threshold voltage of the power-on reset pulse may be optimized to be independent of the absolute temperature and to be insensitive to variations in the power supply voltage and in integrated circuit fabrication process parameters. In addition, the upper threshold voltage of the power-on reset pulse of the present invention is independent of a voltage across a drain and source of any MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with the power-on reset circuit topology of the present invention.

Precision power-on reset circuit with improved accuracy

A non-volatile memory device includes a plurality of MOS transistors 34 and 36 connected to respective word lines 16 and 18 to allow individual pages of memory stored in the memory cells 8a, 10a and 8b, 10b on the respective word lines 16 and 18 to be erased and erase verified. A method of erasing a page of memory cells includes the steps of applying an erase voltage to one of the MOS transistors 16 and 18 to erase the page of memory cells along the respective word line, and applying an initial erase-inhibit floating voltage to other MOS transistors which are connected to the word lines unselected for page erase. In an erase verify mode, an erase verify voltage is applied to the word line which was selected for page erase in the erase mode, and an erase verify unselect voltage is applied to the word lines which was not selected for page erase.

Scheme for page erase and erase verify in a non-volatile memory array

A method is provided for biasing a NAND array EEPROM during programming to allow the array to be scaled down further before reach punchthrough. The sources of the ground-select transistors of the NAND array are biased at V.sub.cc instead of ground to reduce the voltage drop across the source and drain of the ground-select transistors. As a result, the channel length of the ground-select transistors can be further shortened before punchthrough is obtained, resulting in a higher density EEPROM.

Array VSS biasing for NAND array programming reliability

In the programming of a non-volatile memory device, such as a NAND flash memory device 100, a positive bias voltage V.sub.bias is applied to a bit line 44 to set a respective memory gate 44a in a programmed state. In a further embodiment, the positive bias voltage V.sub.bias is obtained by dividing the select drain gate voltage V.sub.cc using two resistors 56 and 58 connected in series.

Bit line biasing method to eliminate program disturbance in a

A precision power-on reset circuit which is highly insensitive to temperature and process variations includes a self-biased proportional-to-absolute-temperature (PTAT) current generator 4, a base-emitter (V.sub.BE) voltage detector 6, and a bipolar complementary metal oxide semiconductor (BiCMOS) inverter 8, which generates a power-on reset pulse for resetting an application circuit when a power supply voltage is turned on. The power-on reset circuit may further include a complementary metal oxide semiconductor (CMOS) buffer 10 coupled to the BiCMOS inverter 8 to isolate the application circuit from currents in the power-on reset circuit.

Precision power-on reset circuit

A recursive voltage booster circuit is provided for generating a boosted output voltage to be higher than the low power supply potential to drive control gates via row decoder circuits and wordlines in an array of Flash EEPROM memory cells during a Read mode of operation. The voltage booster circuit includes a plurality of recursively connected boosting stages. The lower power supply potential has a voltage of +2.0 volts or lower. The boosted output voltage is significantly higher than what is traditionally available so as to enable reading of Flash EEPROM memory cells in a very low power supply voltage environment.

Recursive voltage boosting technique

Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply. By setting the decode input at zero volts, the voltages at the gates of the boost transistors and of the pass transistor are held at zero volts, thus disabling them. In the preferred embodiment, both the regulation transistors and the discharge transistors are included in the high voltage pass gate.

High voltage NMOS pass gate for integrated circuit with high voltage

A system and method for providing a constant electric field that is insensitive to fluctuations in the power supply to a FLASH EPROM during erasure. The system comprises a plurality of sector source drivers and a power supply insensitive constant current source. Each sector has at least one binary storage element. Each storage element has a source. The sector source drivers couple the at least one source of a sector to be erased to the power supply insensitive constant current source. The power supply insensitive constant current source provides an electric field across the tunneling oxide which is constant and insensitive to fluctuations in the power supply. This improves the wear characteristics and lifetime of the binary storage elements. In addition, this system remedies problems associated with short channel effects, electron trapping, and the use of various voltage sources.

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San Jose, CA, United States of America

Michael S Chung