Other

Advanced Micro Devices Corporation

Michael S C Chung

Kazuhiro Kurihara

Binh Quang Le

Shane Charles Hollmer

Santosh K Yachareni

Michael Allen Van Buskirk

Pau-Ling Chen

Joseph G Pawletko

A switched capacitor controller accurately controls the rise time of an on-chip generated high voltage. An on-chip charge pump is used to generate a high voltage (VPP) from an external power supply voltage (VCC). This high voltage signal (VPP) can be used to program Flash memory cells. A capacitor of a switched capacitor circuit is selectively switched between ground and a given node voltage. This generates a stair-stepped ramp function. The period of the steps is controlled according to a clock signal. This clock signal may be altered to produce the desired period. The voltage increases of the steps is regulated by a reference voltage multiplied by a ratio between two capacitor values. Thereby, the rise-time of the ramp function is accurately controlled as a function of the frequency of the clock signal and the ratio of the two capacitor values.

Switched-capacitor controller to control the rise times of on-chip generated high voltages

A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line charge and hold circuit which is operable to apply a read sense voltage (e.g., about 1.2 volts) to a bit line associated with the drain terminal of a cell of the flash array adjacent to the cell which is sensed, wherein the applied drain terminal voltage is substantially the same as the cell sense voltage (e.g., about 1.2 volts) applied to the drain terminal bit line of the selected memory cell to be sensed. The system further includes a selective bit line decode circuit which is operable to select the bit lines of a memory cell to be sensed and the bit line of an adjacent cell, and a core cell sensing circuit which is operable to sense a core cell sense current at a bit line associated with a drain terminal of the selected memory cell to be sensed during memory read operations, and produce an indication of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.

Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold

The present invention relates to flash memory systems and methods to determine the threshold voltage of core cells. In one exemplary system, there is provided a method of characterizing the high end of the threshold voltage distribution of an array of programmed cells. In accordance with the invention, an exemplary system and method are presented to apply a varying characterization signal operably through a high breakdown voltage periphery donut transistor and wordline drive transistors, which are driven into saturation by a boosted gate voltage which is higher than the applied varying characterization signal, in a manner which provides for the accurate determination of the V of the core cells, through the comparison of the conduction in a reference cell to that of the conduction in a core cell produced by a varying characterization signal applied to the core cell gate.

Ceiling test mode to characterize the threshold voltage distribution of over programmed memory cells

A technique to determine whether multiple memory cells are programmed or erased. After a program or erase operation, respective program or erase verify operations are performed. A logical gate is coupled to measure the state of each memory cell. When all memory cells selected to be programmed or erased are programmed or erased then the output of the logical gate indicates successful program or erase verify. Thus, by using a single logical gate coupled to measure the states of multiple memory cells, only the output of the logical gate need be measured to determine successful program or erase verification of multiple memory cells.

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San Jose, CA, United States of America

Michael S C Chung