Micron Technology Incorporated

Micron Quantum Devices Inc.

Advanced Micro Devices Corporation

Silicon Storage Technology, Inc.

Gould Inc.

Advance Micro Devices, Inc.

Greenliant LLC

Michael S Briner

Frankie F Roohparvar

Christophe J Chevallier

Fariborz F Roohparvar

Hieu Van Tran

Jack Frayer

William Saiki

Nader A Radjy

Michael Allen Van Buskirk

Darrell D Rinerson

Tam Minh Nguyen

James C Yu

Eugene Feng

Paul I Suciu

Fredrik Buch

Pearl P Cheng

Babu L Jain

Pardeep K Jain

A time domain voltage step down capacitor based circuit has an oscillating circuit for generating a clock signal. The circuit also has a capacitor based charge pump circuit for receiving the clock signal and an input voltage signal having an input current and generates an output voltage signal, less than the input voltage signal and an output current greater than the input current. The circuit further comprises a comparator circuit for receiving the output voltage signal, as a first input signal thereto, and a reference voltage signal as a second input signal thereto and compares the first input signal to the second input signal and generates a control signal in response thereto. Finally the control signal is supplied to the oscillating circuit to control the generating of the clock signal.

Time domain voltage step down capacitor based circuit

A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.

High speed and high precision sensing for digital multilevel non-volatile memory system

A fast-sensing amplifier for a flash memory comprised of a plurality of floating-gate memory devices and having a column line selectively coupled to the devices is disclosed. The column line is quickly discharged to ground before a read-biasing and amplifying circuit quickly pulls up the line to the read-bias potential at a particular memory device. This potential is compared to a sense-reference potential by a differential amplifier within the fast-sensing amplifier. The binary state of the particular memory device is provided as the output of the fast-sensing amplifier.

Fast-sensing amplifier for flash memory

An integrated circuit memory device has a memory array and a non-volatile register for storing a stored signal. A bus is connected to the device for supplying an externally supplied signal to the device. A comparator compares the stored signal and the externally supplied signal and provides access to the memory array in response to the comparison.

Memory unit having programmable device ID

Read-biasing and amplifying system

Differential sense amplifier for multilevel non-volatile memory

A digital multilevel non-volatile memory integrated system includes an apparatus and method for high voltage, high precision pulsing generation. A voltage generator includes a low voltage high speed generator, a low voltage to high voltage high speed level translator, and a high voltage driver. A precise and stable high voltage level is attained across power supply, process, or temperature variation. The power may be optimized at the high voltage supply as tradeoff with power in the low voltage supply. A ping-pong operation sets up a high voltage level and the high voltage pulsing is output in a ping-pong fashion. A slew rate control circuit slows the input to achieve faster settling times. The high voltage is shaped by low voltage switching, HV fast switching and ramp circuit control. The high voltage pulsing may be fast and precise to permit real time control of the pulse parameters to adapt to memory cell attributes.

High voltage pulse method and apparatus for digital multilevel non-volatile memory integrated system

Feedback biasing integrated circuit

An integrated circuit for concurrent flash memory. The circuit has an uneven array architecture including a pair of arrays of a first size, and a pair of arrays of a second size. The arrays and are cooperatively linked in a manner which allows certain arrays to be read while other arrays are concurrently programmed or erased. The uneven array architecture of circuit provides increased flexibility of bank size combinations for concurrent read and program/erase operation.

Integrated circuit for concurrent flash memory with uneven array architecture

A fast-sensing amplifier for a flash memory including a plurality of floating-gate memory devices and having a column line selectively coupled to the devices is disclosed. The column line is quickly discharged to ground before a read-biasing and amplifying circuit quickly pulls up the line to the read-bias potential at a particular memory device. This potential is compared to a sense-reference potential by a differential amplifier within the fast-sensing amplifier. The binary state of the particular memory device is provided as the output of the fast-sensing amplifier.

First and second flash memory cells or transistors, operating in the linear region of operation, are provided with different threshold values by providing different charges on their respective floating gates. The first of the pair of flash memory transistors is &ldquo;over-erased&rdquo; until it has a negative threshold voltage so that the first flash memory transistor is rendered permanently conducting when its control gate and source are at V . Circuitry is provided for connecting the first and second flash memory transistors in parallel circuits in which equal current values are generated in an equilibrium condition. Circuitry for sensing a voltage in each of the parallel circuits is provided to determine any imbalance in current values and provide an output voltage which may be used as an reference value when the currents are in equilibrium. Circuitry is provided for sensing variations in the output voltage to vary the current through one of the flash memory transistors to bring the currents into equilibrium when the output voltage varies from the reference value provided at equilibrium. The control gate of the first (over-erased) flash memory transistor is connected to the system ground, V to further increase the stability of the reference voltage generator.

Reference voltage generator using flash memory cells

A memory system capable of being configured for optimum performance after fabrication using control parameters stored in non-volatile data storage units. The system includes an array of memory cells, separate from the data storage units, arranged in a multiplicity of rows and a multiplicity of columns, with each cell located in one of the rows being coupled to a common word line and with each cell located in one of the columns being coupled to a common bit line. Control circuitry for controlling memory operations such as programming the memory cells and reading the memory cells when the memory system is in a normal mode of operation. The non-volatile data storage units store control parameter data used by the control means for controlling the memory operations, with the control parameters being modifiable when the memory system is placed in an alternative mode of operation as opposed the normal mode of operation. Once the memory has been fabricated and characterized, the control parameters can be selected for optimum memory performance and loaded into the data storage units.

Memory system having programmable control parameters

A level detection circuit for monitoring the level of a power supply voltage and producing an output signal at power on for resetting various system elements powered by the supply voltage when the supply voltage reaches a predetermined level. The detection circuit, which is powered by the supply voltage includes a voltage reference circuit which produces a reference voltage having a magnitude which is relatively independent of the power supply voltage. A translator circuit functions to produce a translated voltage indicative of the supply voltage magnitude and which is comparable in magnitude to the reference voltage when the supply voltage is at a suitable level such that the system will accept a power on reset pulse. A comparator circuit functions to compare the reference voltage with the translated voltage and cause an associated output circuit to issue the reset pulse. The reset circuit typically includes a one shot circuit, the output of which is logically ORed with the amplified comparator output. The amplified comparator output functions to hold the system elements in a reset state at very low supply voltages and the one shot output functions to reset the system elements once the supply voltage is at a sufficiently high level.

Power level detection circuit

A flash memory array having a reduced number of metal source lines and increased storage density. The cells are arranged in rows and columns, with the cells in a row having their control gates connected to a common word line and the cells in a column having their drains connected to a common bit line. All of the cell sources of the array are connected together with a combination of doped semiconductor and metal lines. The source metal lines are disposed generally in parallel with the bit lines. In order to reduce the number of source metal lines, the lines are spaced apart by, typically, eight, sixteen or more cell columns. The metal source lines define a sub-array therebetween. The array includes a decoder for accessing two cells in different columns of each sub-array during single reading and programming operations. Thus, each sub-array provides two bits of data rather than the customary one bit. The reduced number of metal source lines saves a significant amount of die area with a only a small sacrifice in increased effective source line resistance.

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San Jose, CA, United States of America

Michael S Briner