Intel Corporation

Michael S Bair

Michael Neve De Mevergnies

Hermann Gartler

Raanan Sade

Shlomo Raikin

Robert S Chappell

Igor Yanover

David W Burns

Michael D Tucknott

Prakash Math

Pankaj Raghuvanshi

Leslie A Ong

A chassis platform, such as processor or a system-on-chip (SoC), includes logic to implement a debug chassis security system including a policy generator to control access from a test access port. The policy generator may distribute a debug policy to at least one logic block that locally enforces the debug policy. The debug policy may include a delayed authentication policy in which debug assets are distributed and the chassis platform is initially locked to prevent debug access via the test access port. An authenticated debug user may unlock the chassis platform at a later time to enable debugging operations. The debug policy may also include a live execution policy and an immediate debug policy.

Delayed authentication debug policy

In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.

Regulating atomic memory operations to prevent denial of service attack

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Banks, OR, United States of America

Michael S Bair