Analog Devices,inc.

Analog Devices Global

Analog Devices Global Unlimited Company

Michael S Allen

Joern Soerensen

Thomas A Volpe

John L Redford

Andrew James Higham

Thomas L Evans

Jose Fridman

Mark Banse

Boris Lerner

Xueru Ding

Palle Birk

Abhijit Giri

Paul D Krivacek

Kaushal Sanghai

Michael G Perkins

Moinul Syed

Saurbh Srivastava

Hitesh Anand

Aaron Bauch

A MIMO radar transceiver assembly includes a plurality of transceiver circuit regions and a plurality of antennas. The plurality of antennas include a first transmit antenna coupled to a first transceiver circuit region among the plurality of transceiver circuit regions, a first receive antenna coupled to the first transceiver circuit region, a second transmit antenna coupled to a second transceiver circuit region among the plurality of transceiver circuit regions, and a second receive antenna coupled to the second transceiver circuit region. At least one of the second transmit antenna and the second receive antenna is interleaved between the first transmit antenna and the first receive antenna. Interleaving of the antennas can increase virtual aperture and angular resolution of the radar system without increasing physical dimensions of the transceiver assembly.

Systems and methods for improved angular resolution in multiple-input multiple-output (MIMO) radar

Digital signal processors often operate on two operands per instruction, and it is desirable to retrieve both operands in one cycle. Some data caches connect to the processor over two busses and internally uses two or more memory banks to store cache lines. The allocation of cache lines to specific banks is based on the address that the cache line is associated. When two memory accesses map to the same memory bank, fetching the operands incurs extra latency because the accesses are serialized. An improved bank organization for providing conflict-free dual-data cache access&#x2014;a bus-based data cache system having two data buses and two memory banks&#x2014;is disclosed. Each memory bank works as a default memory bank for the corresponding data bus. As long as the two values of data being accessed belong to two separate data sets assigned to the two respective data buses, memory bank conflicts are avoided.

Bus-based cache architecture

According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode.

Predicate counter

According to one example embodiment, a direct memory access (DMA) engine and buffer is disclosed. The vector buffer may be explicitly programmable, and may include advanced logic for reordering non-unity-stride vector data. An example MEMCPY instruction may provide an access request to the DMA buffer, which may then service the request asynchronously. Bitwise guards are set over memory in use, and cleared as each bit is read.

DMA vector buffer

A digital baseband processor is provided which receives a system clock generated by a system oscillator and generates a plurality of clock signals from the system clock. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and other modules which may require one of the plurality of clock signals for operation. The digital baseband processor also includes a power management circuit which may power down the system oscillator when modules such as the digital signal processor and microcontroller do not require clock signals derived from the system oscillator. The power management circuit may gate off clock signals to modules when those modules do not require clock signals, without powering down the system oscillator.

Method and apparatus for clock and power control in wireless systems

Methods and apparatus for accessing flash memory in a continued burst mode are provided. The apparatus includes a processor for executing instructions including memory access instructions, the processor generating a next access signal that indicates if a next memory access is in sequence with a current memory access, a memory having a continued burst mode of operation, and a bus interface for controlling access to the memory in response to the memory access instructions. The bus interface unit enables the continued burst mode of the memory while the next access signal is asserted.

Methods and apparatus for utilizing flash burst mode to improve processor performance

In parallel with accesses to a cache made by a core processor, a DMA controller is used to pre-load data from a main memory into the cache. In this manner, the pre-load function can make the data available to the processor application before the application references the data, thereby potentially providing a 100% cache hit ratio since the correct data is pre-loaded into the cache. In addition, if a copy-back cache is employed, the cache memory system can also be configured such that processed data can be dynamically unloaded from the cache to the main memory in parallel with accesses to the cache made by the core processor. The pre-loading and/or post unloading of data may be accomplished, for example, by using a DMA controller to burst data into and out of the cache in parallel with accesses to the cache by the core processor. This DMA control function may be integrated into the existing cache control logic so as to reduce the complexity of the cache hardware (e.g., as compared to a multi-port cache), and to alleviate the difficulty associated with addressing the non-contiguous internal address map of the cache. By employing a DMA controller having flexible address generation and transfer control capabilities, data can be transferred from an atypical memory-mapped entity (e.g., a FIFO buffer of a peripheral) directly to the cache.

Cache system with DMA capabilities and method for operating same

A memory system and a method for operating a memory system are provided. The memory system includes a set of memory banks, logic for calculating a first address in each memory bank from the set of memory banks and a controller receiving a transfer address from a computing device. The controller includes logic for selecting a memory bank from the set of memory banks based on the transfer address and the first addresses of the memory banks, and for mapping the transfer address to a target address in the selected memory bank based on a first address in the selected memory bank. As a result, the set of memory banks has a contiguous memory space.

Method and system for providing a contiguous memory address space

Methods and apparatus are provided for operating an embedded processor system that includes a processor and a cache memory. The method includes filling one or more lines in the cache memory with data associated with a first task, executing the first task, and, in response to a cache miss during execution of the first task, performing a cache line fill operation and, during the cache line fill operation, executing a second task. The cache memory may notify the processor of the line fill operation by generating a processor interrupt or by notifying a task scheduler running on the processor.

Methods and apparatus for improving throughput of cache-based embedded processors

Methods and apparatus are provided for supplying data to a processor in a digital processing system. The method includes holding data required by the processor in a cache memory, supplying data from the cache memory to the processor in response to processor requests, performing a cache line fill operation in response to a chache miss, supplying data from a prefetch buffer to the cache memory in response to the cache line fill operation, and speculatively loading data from a lower level memory to the prefetch buffer in response to the cache line fill operation.

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Austin, TX, United States of America

Michael S Allen