Advanced Micro Devices Corporation

Ati Technologies Ulc

Michael S Alfano

Michael Zhouying Su

Bryan Black

Joe Siegel

Julius Din

Michael Mantor

Gabriel H Loh

Rahul Kumar Agarwal

Neil McLellan

Anwar Kashem

Alan Dodson Smith

Raja Swaminathan

Gabriel Wong

Joseph R Siegel

A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.

Creating interconnects between dies using a cross-over die and through-die vias

Various interposers and method of manufacturing related thereto are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an identification structure to an interposer. The identification structure is operable to provide identification information about the interposer. The identification structure is programmable to create or alter the identification information.

Interposer with identification system

Various interposers and methods of manufacturing related thereto are disclosed. In one aspect, an apparatus is provided that includes an interposer that has a first side and a second side opposite the first side. The first side has a first reticle field and a second reticle field larger than the first reticle field. Plural conductor pads are positioned on the first side in the first reticle field. Plural dummy conductor pads are positioned on the first side in the second reticle field and outside the first reticle field.

Interposer with beyond reticle field conductor pads

Various semiconductor workpieces with selective backside metallizations and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor workpiece that has multiple dies. A backside metallization is fabricated on a first die of the dies but not on a second die of the dies.

Semiconductor workpiece with selective backside metallization

A method of manufacturing is provided that includes fabricating a first plurality of electrically functional interconnects on a front side of a first semiconductor chip and fabricating a first plurality of electrically non-functional interconnects on a back side of the first semiconductor chip. Additional chips may be stacked on the first semiconductor chip.

Thermal management of stacked semiconductor chips with electrically non-functional interconnects

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Austin, TX, United States of America

Michael S Alfano