General Electric Company

University System of Maryland

Pacific Bell

US Government As Represented by the Secretary of the Army

United States of America As Represented by the Secretary of the Air Force

The United States of America As Repr. by the Sec. of the Army, U.S. Army Med. Resr. Inst. of Chem. Defense

Michael S Adler

James E Kohl

Edson X Albuquerque

Bantval J Baliga

William P Kornrumpf

John D Harnden, Jr

Eric J Wildi

Edna F R Pereira

Victor A Temple

George E Possin

Thomas Jeffrey Enderwick

Manuel L Torreno, Jr

Deva N Pattanayak

Paul G Huber

Surinder Krishna

Robert S Scott

Conilee G Kirkpatrick

Peter V Gray

Edna Fr Pereira

Deva N Pattanaya

Edna F Pereira

Robert Koeten

The present invention is directed to various methods for treating organophosphorus poisoning in an animal that is at risk of exposure to an organophosphorus compound or preventing organophosphorus poisoning in an animal that has been exposed to an organophosphorus compound, by administering a therapeutically effective amount of galantamine or a salt thereof, or a biologically active analog, derivative, fragment or variant thereof.

Method of treating organophosphorous poisoning

A method for treating organophosphorous poisoning (OP) comprising administering to a mammal at risk for OP poisoning an OP poisoning-inhibiting amount of galantamine.

A method of treating organophosphorous (OP) poisoning comprising administering to a mammal at risk for OP poisoning an OP poisoning-inhibiting amount of galantamine.

MOSFET-gated bipolar transistor and thyristor integrated devices combining, as the respective turn-on and turn-off control devices, an enhancement mode MOSFET and a depletion mode MOSFET. The gates of the two MOSFETs are connected to a single device gate terminal. The conduction channel of the depletion mode MOSFET is preferably an implanted region. With gate voltage of appropriate polarity applied, the depletion mode MOSFET is non-conducting and the enhancement mode MOSFET is conducting, biasing the included bipolar transistor or thyristor into conduction. With zero gate voltage applied, the depletion mode MOSFET conducts and the enhancement mode MOSFET is non-conducting, turning off the included bipolar transistor or thyristor. Significantly, only a single polarity gate input signal is required.

MOSFET-gated bipolar transistors and thyristors with both turn-on and

The present invention relates generally to insulated gate transistors and more particularly, to laterally implemented insulated gate transistors having improved current capacity and improved immunity to latch-up. Specifically, it has been found that a lateral insulated gate transistor fabricated on a heavily doped substrate such as a p+ substrate exhibits improved current density. Further, the inclusion of an additional heavily doped region such as a P+ region proximate the base region contributes to improved latch-up immunity within the device.

Lateral insulated gate bipolar transistors with improved latch-up

Premature avalanche breakdown resulting from high electric fields produced by metal interconnections crossing underlying high conductivity regions of an integrated circuit is eliminated by selectively providing discontinuities in the high conductivity regions underlying the metal interconnection paths.

High voltage integrated circuits

An integrated circuit with a substrate of one conductivity type and a drift layer on the substrate of opposite conductivity type includes a high voltage semiconductor device, such as a P-N diode, with a first main device region of the opposite conductivity type adjoining the drift layer and a second main device region of the same conductivity type as the substrate adjoining the drift layer. The high voltage semiconductor device is electrically isolated from other devices through the incorporation into the integrated circuit of an isolation region adjoining the substrate and surrounding the high voltage device. Electrical isolation of the high voltage device from the substrate is achieved by interposing a highly-doped buried layer of the opposite conductivity type between the second main device region and the substrate so as to prevent current carrier injection from the second main device region into the substrate. A field gate is included in the high voltage device, being insulatingly spaced from the drift layer, situated between the buried layer and the first main device region, and electrically shorted to the second main device region. The field gate prevents the buried layer from rising dangerously high in voltage while the device is in a reverse blocking mode by pinching off current flow in the drift layer that would otherwise raise the voltage of the buried layer. Consequently, avalance breakdown between the buried layer and the above-situated second main device region is avoided.

High voltage integrated circuit devices electrically isolated from an

An integrated circuit in which a large potential can be maintained between the source of the device and the substrate on which this device and other devices are fabricated is described. The circuit employs a minority carrier sink region to remove minority carriers from the gate region of a MOS depletion device. The sink region is shielded from the substrate by a buried layer which prevents punch-through between the sink region and the substrate.

High-voltage pull-up device

A switch is provided wherein a piezoelectric bimorph element is used to provide many separately controllable, closely spaced switchable contacts. The element includes at least two oppositely extending fingers connected by a common spine. The element spine is mounted to a case with the fingers spaced from an inner case surface. Electronic circuit means are mounted on the element spine for applying a separate electrical potential to each of the element fingers. A separate movable electrical contact is disposed on each of the element fingers spaced from the spine and insulated from the means for applying the separate electrical potentials to the fingers. A separate stationary contact is provided on an inner case surface opposite each of the movable contacts. In operations, a separate electrical potential is applied to each of the element fingers for selectively causing each finger to deflect and force its movable contact into electrical connection with the opposing stationary contact.

Piezoelectric switch

A switch is provided wherein a piezoelectric bimorph element is used to provide many separately controllable, closely spaced switchable contacts. The element includes at least two oppositely extending fingers connected by a common spine. The element spine is mounted to a case with the fingers spaced from an inner case surface. Electronic circuit means are mounted on the element spine for applying a separate electrical potential to each of the element fingers. A separate movable electrical contact is disposed on each of the element fingers spaced from the spine and insulated from the means for applying the separate electrical potentials to the fingers. A separate stationary contact is provided on an inner case surface opposite each of the movable contacts. In operation, a separate electrical potential is applied to each of the element fingers for selectively causing each finger to deflect and force its movable contact into electrical connection with the opposing stationary contact.

A solid state composite control circuit includes a normally-off gating device connected in series with a normally-on high voltage semiconductor device so that the combination operates as a normally-off high power semiconductor device. The control device is a low voltage semiconductor device, which can switch rapidly with very low gate turn-off current during turn-off of the composite circuit. In a particular example, a low voltage, normally-off, MOSFET is connected in series with the cathode of a high voltage, normally-on FCT. In another example, a low voltage, normally-off, MOSFET is connected in series with the source of a high voltage, normally-on JFET. The composite circuit has a very high turn-off gain as well as high dv/dt and di/dt capability.

Composite circuit for power semiconductor switching

Power MOSFET devices useful in synchronous rectifier circuit applications are bidirectional and symmetrical for use in AC circuits, and have low on-resistance, fast switching speed, and high voltage capability. In one embodiment, a planar enhancement-mode diffused MOSFET structure obviates the source-to-base short conventionally included to prevent turn-on of the parasitic bipolar transistor defined by the main terminal regions of one conductivity type and the intermediate base region of opposite conductivity type, by employing within the base region a recombination region having a relatively small lifetime for excess base region majority-carriers in order to inhibit operation of the parasitic bipolar transistor. Another embodiment resembles a pair of conventional, vertical-current, MOSFET unit cells formed symmetrically back-to-back and sharing a common drain region which serves only as an intermediate terminal region not directly connected to any device terminal. To inhibit operation of the several parasitic bipolar transistors and thyristor switching device structures inherent in this embodiment, an ohmic short is provided between the source and base regions of each of the unit cells, and a recombination region having a relatively small lifetime for intermediate terminal region majority-carriers is formed within the intermediate terminal region between the spaced base regions of the unit cells.

Bidirectional, high-speed power MOSFET devices with deep level

Fabrication of an integrated circuit containing complementary, dielectrically-isolated, high voltage semiconductor devices of the lateral-current conduction type involves doping of the voltage-supporting regions of the complementary devices in two steps, in accordance with Lateral Charge Control technology. A first conductivity type dopant is introduced into a semiconductor layer as it is being epitaxially grown, with the dopant concentration being below about 20 percent of the desired final doping concentration of the first conductivity type voltage-supporting region. Ion implantation of further first conductivity type dopant achieves final doping of the first conductivity type voltage-supporting region, while a separate ion implantation of a second conductivity dopant achieves final doping of the second conductivity type voltage-supporting region. For high current silicon devices having voltage-supporting regions thicker than about 5 microns, a fast-diffusing P-conductivity dopant, such as aluminum, forms the P-conductivity type voltage-supporting region for enhancing device current conduction capacity, particularly in bipolar devices, such as IGTs or bipolar transistors.

Fabrication of integrated circuit with complementary,

A beam-addressed memory system for digital memory recording and reading which comprises an electron beam generating and focusing subsystem, an electron detecting subsystem, electronic control and interface circuit means, and a storage medium consisting essentially of a cross-linkable polymeric film having an implanted surface layer of heavy metal ions.

Beam addressed memory system

A P-N diode includes a P.sup.- substrate with a thin N.sup.- epitaxial layer thereon. A P.sup.+ isolation region surrounds the periphery of the N.sup.- epitaxial layer and is integrally connected to the P.sup.- substrate. An N.sup.+ cathode region extends into the N.sup.- epitaxial layer from the upper surface of such layer. A P.sup.+ anode region extends into the N.sup.- epitaxial layer from its upper surface and surrounds the N.sup.+ cathode region. A further P.sup.+ region extends into the N.sup.- epitaxial layer from its upper surface and surrounds the N.sup.+ cathode region, and, in turn, is surrounded by the P.sup.+ anode region. The further P.sup.+ region is biased at the same potential as the P.sup.- substrate. An N.sup.+ buried layer is situated between the P.sup.- substrate and the N.sup.- epitaxial layer, beneath the P.sup.+ anode region, and surrounds the N.sup. + cathode region. An N.sup.+ sinker region extends into the N.sup.- epitaxial layer from its upper surface and terminates in integral contact with the N.sup.+ buried layer, the N.sup.+ sinker region surrounding the P.sup.+ anode region, and, in turn, being surrounded by the P.sup.+ isolation region. The N.sup.+ buried layer reduces parasitic currents in the P-N diode, and the further P.sup.+ region, appropriately biased, enables the P-N diode to block current at high reverse voltages. An N-P-N transistor is structurally similar to the P-N diode, having an additional N.sup.+ emitter region diffused into a P.sup.+ base region, corresponding to the P.sup.+ anode region of the P-N diode.

Growing community of inventors

Schenectady, NY, United States of America

Michael S Adler