Infineon Technologies Ag

Michael Röhner

Walter Hartner

Nicolas Nagel

Rainer Bruchhaus

Gerhard Enders

Thomas Mikolajick

Stefano Aresu

Marco Faricelli

Matthias Krönke

A semiconductor wafer includes dielectric regions of different thicknesses, some of the dielectric regions being thinner and other ones of the dielectric regions being thicker. The semiconductor wafer further includes a stress circuit operable to stress at least one of the dielectric regions internally within the semiconductor wafer for assessing dielectric reliability. A corresponding method of internally assessing dielectric reliability of a semiconductor technology is also provided.

Circuit and method for internally assessing dielectric reliability of a semiconductor technology

Capacitor devices are formed in an essentially vertically extending fashion in order to achieve an essentially three-dimensional configuration or a configuration extending into the third dimension. A contacting of plug regions is performed after producing the capacitor devices. Such capacitor devices provide an increased integration density in a semiconductor memory device.

Method for fabricating a semiconductor memory device

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Munich, Germany

Michael Röhner