Globalfoundries Inc.

Other

Michael Ronald Otto

Nigel Chan

Germain Bossu

Jan Höntschel

Friedrich Goetz

Guenther Jung

Peter Benjamin Volk

Maximilian Jüttner

Roderich Suessmuth

Christoph Rainer Gerhard Mueller

The present disclosure generally relates to semiconductor structures and, more particularly, to back gate tuning circuits and methods of manufacture. The method includes applying a voltage to a back gate of a device; and selectively controlling the applied voltage to deactivate at least one trap within an insulating layer of the device to reduce noise contribution from the at least one trap.

Back gate tuning circuits

The present disclosure relates to semiconductor structures and, more particularly, to circuits with logical back-gate switching and methods of operation. The circuit includes at least one front-gate contact and digital back-gate potentials for logical function implementation on a back side of at least one device. The digital back-gate potentials are switchable between two logic levels.

Semiconductor structure with back-gate switching

A device including a plurality of static random-access memory (SRAM) bitcells arranged in rows and columns, wherein the SRAM bitcells comprise fully depleted silicon-on-insulator field effect transistors (FDSOI-FETs). The FDSOI-FETs comprise P-channel-pull-up-transistors, wherein each P-channel-pull-up-transistor comprises a back gate. The device further includes a plurality of bitlines, wherein each bitline is electrically connected to the SRAM bitcells of one of the columns and a plurality of wordlines, wherein each wordline is electrically connected to the SRAM bitcells of one of the rows. The device further includes a bitline control circuit configured to select at least one column for writing, wherein during a write operation a first control signal is applied to the back gates of the P-channel-pull-up-transistors of the at least one column selected for writing and a second control signal to the back gates of the P-channel-pull-up-transistors of the columns not selected for writing.

Device comprising a plurality of FDSOI static random-access memory bitcells and method of operation thereof

A method and apparatus for including human readable text in a semiconductor design which is both machine readable for printing on a wafer and human readable from the wafer are disclosed that are design rule clean depending on the layer to be printed. Embodiments include receiving a semiconductor design including a layer marker, the layer marker including human readable text; transforming the human readable text to a binary representation; transforming the binary representation to a machine readable two-dimensional barcode; and printing the two-dimensional barcode on a semiconductor wafer.

Rule clean layer marker

A memory array assembly and a method for performing a write operation without disturbing data stored in other SRAM cells are provided. The memory array assembly comprises a plurality of SRAM cells, a plurality of avoid-disturb cells, a plurality of sense amplifiers and a plurality of write drivers. The SRAM cells are arranged in rows and columns, wherein each column is coupled to an avoid-disturb cell, a sense amplifier, and a write driver. The avoid-disturb cell receives a select signal capable of assuming first or second states. An output of the sense amplifier is coupled to an input of the write driver when the select signal is in the first state. A data-in bus is coupled to the input of the write driver if the select signal is in the second state. The write driver then sends the output signal to the SRAM cell.

Memory cell assembly including an avoid disturb cell

A device includes an array of a plurality of memory cells, at least one N-well contact area and at least one P-well contact area. The memory cells are arranged in a plurality of rows and a plurality of columns. Each column includes an N-well region and at least one P-well region. The N-well and P-well regions extend between a first end of the column and a second end of the column. Each N-well contact area electrically contacts at least one of the N-well regions, wherein the N-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column. Each P-well contact area electrically contacts at least one of the P-well regions, wherein the P-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column.

Device including an array of memory cells and well contact areas, and method for the formation thereof

A method comprises writing data to one or more static random access memory (SRAM) cells. Writing data to the one or more SRAM cells comprises applying a first data signal to at least one bit line electrically connected to the one or more SRAM memory cells, electrically disconnecting at least one of a first power supply terminal and a second power supply terminal of each of the one or more SRAM cells from a power supply and applying a word line signal to a word line electrically connected to the one or more SRAM cells. Thereafter, the at least one of the first power supply terminal and the second power supply terminal of each of the one or more SRAM cells is electrically connected to the power source.

Device comprising a plurality of static random access memory cells and method of operation thereof

The present invention relates to peptides, which are useful in treating Staphylococcus infections. More particularly, the inventive peptides interfere with the regulation of the agr system of Staphylococcus species, especially S. aureus, and thereby block the formation of different virulence factors. The inventive peptides comprise at least the amino acid sequence S V X A S Y F, whereby cyclic structures of that kind of peptides are the most potent blocking reagents.

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Dresden, Germany

Michael Ronald Otto