Google Inc.

Wisconsin Alumni Research Foundation

Michael Roger Marty

Dennis Charles Abts

Philip Michael Wells

Marcus Felipe Fontoura

Peter Michael Klausler

Nicholas Andrew Kidd

Charles Acknin

Benjamin Charles Serebrin

Paul Jack Turner

Parthasarathy Ranganathan

Hong Liu

Rama Krishna Govindaraju

Luiz Andre Barroso

Liqun Cheng

Lawrence Elias Greenfield

James Laudon

Andrew Gallatin

Joel Scherpelz

Christopher Alfeld

Marc De Kruijf

Prashant R Chandra

Weihuang Wang

Mark Donald Hill

David Allen Wood

Nandita Dukkipati

Angela Chen

Michael Mansfield Swift

Xiaoming Wang

Gautam Kumar

William Evans

Hassan Wassel

Adi Avidor

Nicholas McDonald

Neelesh Bansod

Frank Dabek

Daniel Jonathan Peng

Luke Yen

Kevin E Moore

Jayaram Bobba

Haris Volos

Nicholas Mcdonald

A system includes a first processor configured to analyze packets received over a communication protocol system and determine one or more congestion indicators from the analysis of the data packets, the one or more congestion indicators being indicative of network congestion for data packets transmitted over a reliable transport protocol layer of the communication protocol system. The system also includes a rate update engine separate from the packet datapath and configured to operate a second processor to receive the determined one or more congestion indicators, determine one or more congestion control parameters for controlling transmission of data packets based on the received one or more congestion indicators, and output a congestion control result based on the determined one or more congestion control parameters.

Rate update engine for reliable transport protocol

A method includes for each processed interrupt: identifying an interrupt associated with a first interrupt number; determining that the interrupt is designated as a special interrupt, the special interrupt being an interrupt to be translated to a different interrupt number only if the hardware processor is in user mode; determining a current execution mode for the hardware processor; for each interrupt in operating system mode, delivering the interrupt as the first interrupt number; and for each interrupt in user mode: translating the first interrupt number to a second interrupt number; and delivering the interrupt as the second interrupt number, wherein the current execution mode is determined to be an operating system mode for at least one of the interrupts, and the current execution mode is determined to be a user mode for at least an additional one of the interrupts.

User mode interrupts

A computing system dedicates one or more processing units, such as cores, for the purposes of packet processing software, wherein other processing units simultaneously run application software. In some examples, the system uses dynamic load information to dynamically increase and decrease the number of processing units dedicated to packet processing. The system may further include a mechanism for establishing shared-memory regions for interacting with other applications' users. The shared memory mechanisms provide an abstraction of per-application 'command' and 'completion queues'. The system may poll per-application command queues for detecting the arrival of new requests. The mechanism also provides detection of application termination, as well as an ability for an application to expose portions of its address space for the reception and transmission of data. In some examples, the system further includes a framework for executing software-defined handlers inline with threads that run packet processing and transport software.

System and method for hardware-independent RDMA

An example method includes during execution of a software application by a processor, receiving, by a copy processor separate from the processor, a request for an asynchronous data copy operation to copy data within a memory accessible by the copy processor, wherein the request is received from a copy manager accessible by the software application in a user space of an operating system managing execution of the software application; in response to the request, initiating, by the copy processor, the asynchronous data copy operation; continuing execution of the software application by the processor; determining, by the copy processor, that the asynchronous data copy operation has completed; and in response to determining that the asynchronous copy operation has completed, selectively notifying, by the copy processor, the software application that the asynchronous copy operation has completed.

Asynchronous copying of data within memory

Systems and methods for updating an application without a restart are provided. A processor can start a second application instance while a first application instance is still executing. The first application instance can transfer a first set of state information to the second application instance. The second application instance can declare its readiness for activation in response to completion of the transfer. The first application instance can deactivate in response to the declaration. Deactivation includes transferring a second set of state information from the first application instance to the second application instance and releasing single-access resources. The second application instance can activate. Activation includes receiving the second set of state information, and accessing the single-access resources. The second application instance can declare that activation is complete in response to completion of the activation. The first application instance can terminate in response to the declaration.

Transparent upgrade of a system service or application

The expansion of a network by converting the network from a 2-stage folded Clos network to a 3-stage folded Clos network can be cost prohibitive. The system and methods described herein relate to a hybrid network topology. More particularly, the disclosure describes a hybrid topology having internal switches configured in a multidimensional topology configuration. Each of the internal switches are connected to the network hosts with a folded Clos topology.

Hybrid Clos-multidimensional topology for data center networks

A method includes performing one or more operations as requested by a thread executing on a processor, the thread having a thread context; receiving a park request from the thread, the park request received following a request from the thread for a low latency resource, wherein the cache response time is less than or equal to a resource response threshold so as to allow the thread context to be stored and retrieved from the cache in less time than the portion of time it takes to complete the request for the low latency resource; storing the thread context in the cache; detecting that the resume condition has occurred; retrieving the thread context from the cache; and resuming execution of the thread.

Low latency thread context caching

Systems and methods include a distributed system that uses a declarative language to separate application logic from the network technology used to communicate. For example, in a system with a plurality of processing nodes, each processing node may include at least one processor, a networking layer for communicating with other processing nodes, and a memory storing instructions that, when executed by the at least one processor, cause the processing node to perform operations. The operations may include receiving a processing plan using the networking layer and analyzing the processing plan to determine a service to perform and a number of inputs anticipated for the service. The operations may also include performing the determined service. The processing plan defines a processing tree comprising a subset of the plurality of processing nodes, the processing tree having unidirectional communication from the root to a final level of the tree.

Network-independent programming model for online processing in distributed systems

The present disclosure provides methods and systems to allow user space applications running on different cores to efficiently communicate interrupts between each other without have to enter an OS kernel. In one aspect, a hardware device for delivering inter-processor interrupts is provided. The hardware device includes a memory having a memory space that corresponds to a virtual memory space of a first guest process and a controller coupled to the memory. The controller may be configured to detect when interrupt information is recorded in the memory space. In that regard, the interrupt information is directed to a second guest process associated with a particular CPU core. In response to detecting interrupt information recorded in the memory space, the controller is configured to cause the second guest process to run on a different CPU core without making an operating system call.

OS bypass inter-processor interrupt delivery mechanism

Probabilistic arbitration is combined with distance-based weights to achieve equality of service in interconnection networks, such as those used with chip multiprocessors. This arbitration desirably used incorporates nonlinear weights that are assigned to requests. The nonlinear weights incorporate different arbitration weight metrics, namely fixed weight, constantly increasing weight, and variably increasing weight. Probabilistic arbitration for an on-chip router avoids the need for additional buffers or virtual channels, creating a simple, low-cost mechanism for achieving equality of service. The nonlinearly weighted probabilistic arbitration includes additional benefits such as providing quality-of-service features and fairness in terms of both throughput and latency that approaches the global fairness achieved with age-base arbitration. This provides a more stable network by achieving high sustained throughput beyond saturation. Each router or switch in the network may include an arbiter to apply the weighted probabilistic arbitration.

Probabilistic distance-based arbitration

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Madison, WI, United States of America

Michael Roger Marty