Infineon Technologies Ag

Siemens Aktiengesellschaft

Michael Rogalli

Wolfgang Lehnert

Manfred Schneegans

Evelyn Napetschnig

Johann Gatterbauer

Robert Illing

Werner Robl

Stefan Woehlert

Heiner Bayer

Michael Nelhiebel

Thomas Detzel

Sven Lanzerstorfer

Harry Walter Sax

Maximilian Krug

Johann Gross

Bernhard Weidgans

Stephan Wege

Markus M Kirchhoff

Oswald Spindler

Kurt Matoy

Josef Mundigl

Josef Kirschbauer

Barbara Lehner

Jurgen Fischer

Gunter Didschies

Hans Stelzl

Lars Völkel

Wolfgang Jaeger

Frank Dittrich

Doerthe Groteloh

Dirk Toebben

Erich Hopf

A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.

Chip package and method of forming a chip package

A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280&#xb0; C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40&#xb0;.

Method of forming an aluminum oxide layer, metal surface with aluminum oxide layer, and electronic device

A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.

Semiconductor device having a copper element and method of forming a semiconductor device having a copper element

Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness.

Semiconductor devices and processing methods

An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 &#x3bc;m and a ratio of average grain size to thickness of less than 0.7.

Integrated circuit and method of forming an integrated circuit

According to one embodiment, a method for processing a semiconductor device is provided including forming a final metal layer forming a passivation layer over the final metal layer and structuring the passivation layer and the final metal layer to form a patterned metal layer and a patterned passivation layer, wherein the patterned metal layer includes a pad region covered by the patterned passivation layer.

Method for providing a self-aligned pad protection in a semiconductor device

A photosensitive resist () for coating on a semiconductor substrate or a mask comprises a photo acid generator (D), a solvent (E) and at least two different base polymers, of which a first base polymer comprises cycloaliphatic parent structures (A) which substantially absorb incident light at 248 nm and are substantially transparent to incident light at 193 nm, and a second base polymer comprises aromatic parent structures (B) which substantially absorb incident light at 193 nm and are substantially transparent to incident light at 248 nm. If such a resist () is applied in a coat thickness of from 50 to 400 nm to a substrate and the proportion of the second base polymer having the aromatic parent structure is between 1 and 25 mol %, a relatively high structure contrast, better stability to etching and a reduction of defects are advantageously achieved in an exposure at a wavelength of 193 nm. Exposure over the entire depth range of the resist () is ensured thereby.

Photosensitive lacquer for providing a coating on a semiconductor substrate or a mask

The present invention relates to a process for the back-surface grinding of wafers using films which have a support layer, which is known per se, and an adhesion layer which can be polymerized in steps, and to films which include such an adhesion layer which can be polymerized in steps, and to the use thereof.

Process for the back-surface grinding of wafers

A method for producing metal layers on surfaces of semiconductor substrates includes the step of providing a semiconductor substrate having a surface. In this case, a precursor compound of a metal to be deposited is condensed out on the semiconductor surface and subsequently decomposed thermally. The method makes it possible to fill trenches with a high aspect ratio, it being possible to effectively suppress the formation of voids.

Method for fabricating thin metal layers from the liquid phase

The present invention relates to a dielectric filling for electrical wiring planes of an integrated circuit. The electrical wiring of the integrated circuit comprises a base body on which track and passivation planes can already be disposed; a conductive layer which is disposed on the base body and is patterned in such a manner that it exhibits a first conductor track, a second conductor track and a trench between the first conductor track and the second conductor track; at least one dielectric layer is disposed on the conductive layer and at least partially fills the trench, the preferred material of the dielectric layer being the polymer material polybenzoxazole.

Dielectric filling of electrical wiring planes

A chip card includes a plastic card. A plastic body is disposed in the plastic card and a semiconductor chip is surrounded by the plastic body. Contact strips are electrically connected with the semiconductor chip and are connected to the plastic card. The contact strips have a flexible region near and outside of the plastic body and are advantageously parts of a lead frame. An adhesive which joins the contact strips to the plastic card has at least three layers including a middle layer of flexible material.

Chip card

A method for depositing an SiO.sub.2 layer, which acts as an inter-metal dielectric (IMD), is provided. The method includes the steps of applying to the topography an organodisiloxane which is dissolved in an organic solvent, the organodisiloxane is then polymerized, and the polymer formed is decomposed, the polymer changing in the process to become an SiO.sub.2 -rich layer. The method of the present invention results in SiO.sub.2 layers which achieve an excellent local and global degree of planarization and have a distinctly lower dielectric constant than SiO.sub.2 layers prepared using conventional methods.

Method for forming of a silicon oxide layer on a topography

A radiation-curable reaction resin system, comprising a homogeneous solution of a thermoplastic and a reaction resin, whereby the proportion of the thermoplastic in the solution is approximately 3 to about 50% by weight. The reaction resin system has a stable shelf life. Further, the reaction resin system can be cured by radiation to form a shaped material, comprising a continuous and a discontinuous phase and which exhibits thermoplastic-like behavior.

Growing community of inventors

Rottenburg, Germany

Michael Rogalli