Arm Limited

Michael Robert Nonweiler

David Hennah Mansell

Luc Orion

Simon Charles Watt

Nicolas Chaussade

Lionel Belnet

Christopher Bentley Dornan

Stephane Eric Sebastien Brochier

Dominic Hugo Symes

David Walter Flynn

David James Seal

Peter Guy Middleton

Wilco Dijkstra

Timothy Holroyd Glauert

A method and apparatus for processing data when an interrupt is received during processing of a function at a point during the processing at which a portion of the function has been processed then a control parameter is accessed. In response to a control parameter having a value indicting that the function has idempotence, processing of the function is stopped, and information on progress of the function is discarded such that following completion of the interrupt the portion of the function that has already been processed is processed again. In response to the control parameter having a value indicating that the function does not have idempotence, processing of the function is suspended without discarding information on progress of the function that has already been processed such that following completion of the interrupt the processing is resumed from a point that it reached when it was suspended.

Handling interrupts in data processing

A method of processing data comprising: processing a function using a processor operable to perform a plurality of functions, the processor having interrupts enabled; receiving an interrupt at the processor; suspending processing of the function; accessing at least one control parameter, the at least one control parameter indicating whether processing of the function should be resumed from the point where it was interrupted or whether the function should be repeated following the interrupt; following completion of the interrupt continuing processing of the function either at a start of the function or at a point at which it was interrupted dependent upon the control parameter. A function being an application, a thread, a system software routine, or multiple processing steps defined by software.

Method and apparatus for processing data related to handling interrupts in data processing

The present invention provides a technique for swapping data values within a data word. In particular, a single endian reverse instruction is provided to cause independent swap operations to be performed on particular sections of an input data word. The data processing apparatus of the present invention comprises a data processing unit for executing instructions which is responsive to the endian reverse instruction to apply an endian reverse operation to an input data word Rm comprising a plurality of data values. The endian reverse operation yields a result data word Rd given by: treating the input data word as consisting of a plurality of input sections, the result data word having a corresponding plurality of result sections, at least one input section comprising a plurality of data values; and for at least one of the input sections comprising a plurality of data values, performing an independent swap operation on the data values within that input section to form the result data word Rd in which the corresponding result section has its data values swapped with respect to that input section. This provides a particularly efficient technique for providing endian reversal functionality within a data processing apparatus supporting a variety of data structures, such as packed halfwords, zero extended halfwords, sign extended halfwords, etc.

Data processing apparatus and method for utilizing endianess independent data values

Handling interrupts in data processing of data in which only a portion of a function has been processed

In a data processing system using multiple operating systems, an interrupt which itself may be interrupted by a subsequent interrupt which will be serviced in a different operating system, guards itself against being overlooked when that subsequent interrupt has been handled by starting a stub interrupt handling routine in that other operating system before executing the main handling routine in the originating operating system. Thus, the stub interrupt handling routine will be recognised in the other operating system irrespective of other interrupt events which may occur and accordingly the interrupted interrupt handling may be restarted.

Handling multiple interrupts in a data processing system utilising multiple operating systems

The present invention provides a data processing apparatus and method for controlling access to a memory in the data processing apparatus. The apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain. The processor is operable such that when executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A memory is operable to store data required by the processor and comprises secure memory for storing secure data and non-secure memory for storing non-secure data, the processor being operable to issue a memory access request when access to an item of data in the memory is required. At least one memory management unit is provided which is operable, upon receipt of the memory access request from the processor, to perform conversion of a virtual address specified by the memory access request to a physical address. A first set of tables is provided, each table in the first set containing a number of first descriptors, each first descriptor containing at least a virtual address portion and a corresponding intermediate address portion, and a second set of tables is also provided, with each table in the second set containing a number of second descriptors, each second descriptor containing at least an intermediate address portion and a corresponding physical address portion. The second set of tables are managed by the processor when operating in a privileged mode which is not a non-secure mode, and hence remains secure. The at least one memory management unit is then operable to cause predetermined tables in the first and second set to be referenced to enable the conversion of the virtual address specified by the memory access request to a physical address.

Apparatus and method for controlling access to a memory

An apparatus for processing data, the apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including at least one secure mode being a mode in the secure domain; and at least one non-secure mode being a mode in the non-secure domain. When the processor is executing a program in a secure mode, the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor further includes a non-secure translation table base address register and a secure translation table base address register operable in the non-secure and secure domain, respectively, to indicate a region of memory storing either non-secure or secure domain memory mapping data defining how virtual addresses are translated to physical addresses within either the non-secure or secure domain.

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Cambridge, United Kingdom

Michael Robert Nonweiler