International Business Machines Corporation

Adeia Semiconductor Bonding Technologies Inc.

Adeia Semiconductor Solutions LLC

Michael Rizzolo

Lawrence Alfred Clevenger

Benjamin David Briggs

Christopher J Penny

Chih-Chao Yang

Theodorus E Standaert

Bartlet H Deprospo

Huai Huang

Leigh Anne H Clevenger

Nicholas Anthony Lanzillo

Hosadurga K Shobha

Ashim Dutta

Aldis G Sipolins

Takashi Ando

Cornelius Brown Peethala

Jonathan Hudson Connell, Ii

Nalini Kanta Ratha

Prasad Bhosale

Takeshi Nogami

Koichi Motoyama

Oscar Van Der Straten

Alexander Reznicek

James H Stathis

Daniel C Edelstein

Marc Adam Bergendahl

Maryam Ashoori

Saba Zare

Ruilong Xie

Terry Allen Spooner

John Christopher Arnold

Roger Allan Quon

Raghuveer Reddy Patlolla

Jay William Strane

Kisup Chung

Gangadhara Raja Muthinti

Liying Jiang

Isabel Cristina Chu

Son Van Nguyen

Ruqiang Bao

Sean David Burns

Deepika Priyadarshini

Spyridon Skordas

James John Kelly

Jonathan R Fry

Chao-Kun Hu

Gen Tsutsui

Tuhin Sinha

Sebastian Naczas

Justin A Canaperi

Oleg Gluschenkov

Fee Li Lie

Injo Ok

Jon Michael Slaughter

Donald Francis Canaperi

Christopher Joseph Waskiewicz

Kevin W Brew

Nicole A Saulnier

Shyng-Tsong Chen

Joe Lee

Hao Tang

Dominik Metzler

Hari Prasad Amanapu

Mona Abdulkhaleg Ebrish

Eric Raymond Evarts

Virat Vasav Mehta

Christoper J Penny

Leigh Anne Hodges Clevenger

Kangguo Cheng

Bruce Bennett Doris

Brent A Anderson

Juntao Li

Bahman Hekmatshoartabari

Michael J Ellsworth, Jr

Madhusudan K Iyengar

Robert E Simons

Richard C Chu

Levi A Campbell

Julien Frougier

Lars W Liebmann

Ekmini Anuja De Silva

Ravi Nair

Dimitri Houssameddine

Yi Song

Patrick D Watson

James Jay McMahon

Devika Sarkar Grant

Bassem M Hamieh

Benjamin D Briggs

Nicholas V LiCausi

Max S Cioban

Semiconductor devices including a super via connection between levels are provided. The semiconductor device can include a first interlevel dielectric layer, a back-end-of-line (BEOL) interconnect structure disposed in the first interlevel dielectric layer, a second interlevel dielectric layer disposed on a first portion of the first interlevel dielectric layer, a third interlevel dielectric layer disposed on the second interlevel dielectric layer, and a super via disposed on a second portion of the first interlevel dielectric layer, wherein a first end of the super via is connected to the BEOL interconnect structures and wherein a second end of the super via opposite the first end of the super via is a distance from the first interlevel dielectric layer larger than a height distance of the second interlevel dielectric layer.

BEOL interconnect subtractive etch super via

An MRAM device is provided. The MRAM device includes a first dielectric cap layer formed on an underlying layer, a second dielectric cap layer formed on the first dielectric cap layer, the first dielectric cap layer including a lower-κ material than that of the second dielectric cap layer. The MRAM device also includes a bottom electrode contact (BEC) formed through the first dielectric cap layer and the second dielectric cap layer, an MRAM stack formed on the BEC, and wherein the second dielectric cap layer surrounds an upper portion of the BEC.

Layered bottom electrode dielectric for embedded MRAM

A semiconductor structure comprises an active device stack comprising one or more layers, the one or more layers comprising a top electrode. The semiconductor structure also comprises an additional layer disposed over the active device stack, an encapsulation layer surrounding the active device stack and the additional layer, and a contact to the top electrode coupled to the additional layer.

Metal hard mask integration for active device structures

Aspects of the invention are directed to a method of forming an integrated circuit. Both a dielectric layer and a bottom contact are formed with the bottom contact disposed at least partially in the dielectric layer. The bottom contact is subsequently recessed into the dielectric layer to cause the dielectric layer to define two sidewalls bordering regions of the bottom contact removed during recessing. Two sidewall spacers are then formed along the two sidewalls. A landing pad is formed on the recessed bottom contact and between the two sidewall spacers. Lastly, an additional feature is formed on top of the landing pad at least in part by anisotropic etching. In one or more embodiments, the additional feature includes a magnetic tunnel junction patterned at least in part by ion beam etching.

Patterning magnetic tunnel junctions and the like while reducing detrimental resputtering of underlying features

A back side contact structure is provided that directly connects a first electrode of a MRAM, which is present in a back side of a wafer, to a source/drain structure of a transistor. The back side contact is self-aligned to the source/drain structure of the transistor as well as to the first electrode of the MRAM. The close proximity between the MRAM and the source/drain structure increases the speed of the device. MRAM yield is not compromised since no re-sputtering of back side contact metal onto the MRAM occurs.

MRAM integration with self-aligned direct back side contact

A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

Selective ILD deposition for fully aligned via with airgap

A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a top contact, a hard mask layer below the top contact, and a magnetic tunnel junction (MTJ) below the hard mask layer. The MRAM cell further comprises a diffusion barrier below the MTJ, a bottom contact below the diffusion barrier, and a magnetic liner arranged around the bottom contact.

Selectively biasing magnetoresistive random-access memory cells

One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target sorting bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.

Optimizating semiconductor binning by feed-forward process adjustment

A cross-point SOT-MRAM cell includes: a first SHE write line; a second SHE write line non-colinear to the first SHE write line; a cross-point free layer comprising a first free layer, a second free layer, and a dielectric layer disposed between the first and the second free layers, the cross-point free layer configured to store a magnetic bit and located between and in contact with both the first SHE write line and the second SHE write line; and a remote sensing MTJ located in a vicinity of the cross-point free layer, wherein a free layer sensor of the remote sensing MTJ is in contact with one of the first SHE write line and the second SHE write line.

Spin orbit-torque magnetic random-access memory (SOT-MRAM) with cross-point spin hall effect (SHE) write lines and remote sensing read magnetic tunnel-junction (MTJ)

A method for fabricating a semiconductor device includes forming a conductive shell layer along a memory stack and a patterned hardmask disposed on the memory stack, and etching the patterned hardmask, the conductive shell layer and the memory stack to form a structure including a central core surrounded by a conductive outer shell disposed on a patterned memory stack.

Pillar-based memory hardmask smoothing and stress reduction

A system for a touch screen interface that includes a coating including a plurality of a touch activated microchips; and a projector for projecting a light image onto the coating that is applied to a touch screen substrate. The system also includes an image calibrator that calibrates touch activated microchips in the coating to features of the light image projected onto the coating. The system further includes a receiver for receiving signal from the touch activated microchips when said feature of the light image is activated.

Paint on micro chip touch screens

An electrical device includes a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parallel lengths, and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines.

Electrical device having conductive lines with air gaps therebetween and interconnects without exclusion zones

A low temperature deposited (400&#xb0; C. or less) dielectric passivation layer is formed on physically exposed surfaces of a material stack including a multilayered magnetic tunnel junction (MTJ) pillar and a top electrode. A laser anneal is then performed to improve the physical and chemical properties of the low temperature deposited dielectric passivation layer, without negatively impacting the multilayered MTJ pillar.

Laser anneal for MRAM encapsulation enhancement

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Albany, NY, United States of America

Michael Rizzolo