Averatek Corporation

Michael Riley Vinson

Shinichi Iketani

Sunity Kumar Sharma

Haris Basit

Mihir Reddy

Calvin Chen

Divyakant P Kadiwala

Gary Lawrence Borges

Devices and methods for forming an electrical circuit out of a conductor embedded in two layers of substrate are disclosed. Portions of the two layers of substrate and the conductor are removed, forming a cavity through the two layers and the conductor. A blocker material is deposited along the wall of the cavity. A portion of the blocker material and adjacent layer of the substrate is removed forming another cavity in contact with a part of the conductor. A surface of the second cavity is then electroless plated by a conductive metal to form part of the electrical circuit.

Method of manufacture for embedded IC chip directly connected to PCB

Systems, methods, and devices related to catalyzed metal foils are disclosed. Contemplated metal foils have a bottom surface, preferably roughened to Ra of at least 0.1 μm, bearing a catalyst material. The metal foils are etchable, typically of aluminum or derivative thereof, and is less than 500 μm thick. Methods and systems for forming circuits from catalyzed metal foils are also disclosed. The catalyst material bearing surface of the metal foil is applied to a substrate and laminated, in some embodiments with a thermoset resin or thermoplastic resin therebetween or an organic material first coating the catalytic material. The metal foil is removed to expose the catalyst material, and a conductor is plated to the catalyst material.

Catalyzed metal foil and uses thereof to produce electrical circuits

The present invention relates to methods and systems for deposition of metal conductors using asymmetrical electrolytic plating, in which one surface (e.g., top) of a substrate is coated with an electrical conductor, and an opposite (e.g., bottom, or other) surface of which is not coated. A channel is formed between the two sides of the substrate, passing through the substrate and, in some embodiments, passing through the conductor. Electrolytic plating is performed such that metal is deposited from the edge of the conduct proximal to the channel, along the side walls of the channel, and up to, and in some embodiments on to, the other side of the substrate. Use of etching or plate resist layers are also contemplated.

Asymmetrical electrolytic plating for a conductive pattern

Compositions and methods for coupling metals to aluminum surfaces are provided. The compositions are prepared as aqueous solutions or suspensions, and can be applied to the aluminum surface using conventional printing techniques. Rheology of the printable composition can be adjusted to provide a gel or a cream. Curing steps, if necessary, are performed at low temperatures that are compatible with plastic/polymer components of mass produced devices, such as aluminum RFID antennae.

Printable surface treatment for aluminum bonding

Devices, methods, and systems for forming an electrical circuit out of a conductor embedded in two layers of substrate are disclosed. Portions of the two layers of substrate and the conductor are removed, forming a cavity through the two layers and the conductor. A blocker material is deposited along the wall of the cavity. A portion of the blocker material and adjacent layer of the substrate is removed forming another cavity in contact with a part of the conductor. A surface of the second cavity is then electroless plated by a conductive metal to form part of the electrical circuit.

Three dimensional circuit formation

Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.

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Sunnyvale, CA, United States of America

Michael Riley Vinson