Seagate Technology Incorporated

Michael Richard Fabry

Scott Edward Ryun

Paul Allison Beatty

Dipeshkumar J Purani

Paul S Tyler

Jackson Wagner Nichols

Christopher L Hill

Rory Stephan Goodman

Silvia De Vito Luebben

Ted Randal McDonald

Dale Herbert Erickson

Kenneth Eugene Schultz

Michael John Peterson

Hassan Rezayat

Sean M Horgan

William Bradford Green

John Francis Fletcher

Chau Chin Low

Terry Junge

Oscar Woo

Robert Michael Echols

Jonathan E Olson

Tiang Fee Yin

Choon An Aw

Electronic devices that include a composition that can generate a gaseous oxidizing agent component; and a generating device configured to actively cause the composition to generate the gaseous oxidizing agent component. The generating device includes at least one metal-air battery that is in electrical communication with a power source that is configured to apply power to the metal-air battery according to a predetermined time interval to recharge the metal-air battery to generate the gaseous oxidizing agent component.

Electronic device that includes a composition that can actively generate and release a gaseous oxidizing agent component into an interior space of the electronic device, and related subassemblies and methods

The present disclosure relates to electronic devices that include a composition that actively generates a gaseous oxidizing agent component within the interior gas space of the electronic device. The present disclosure also involves related methods.

A method for manufacturing electrical connector assemblies is disclosed. The electrical connector assemblies include an electrical interposer and a first electrical receptacle. The method includes positioning a fixture coupled to or including an array of the first electrical receptacles such that each of the first electrical receptacles aligns with one of the electrical interposers on an assembly with an array of the electrical interposers. The method further includes reflowing solder to mechanically and electrically couple the array of the first electrical receptacles to the array of the electrical interposers.

Methods for making electrical connectors with an electrical interposer

A printed circuit board includes a substrate and at least one electrical circuit provided at least partially on a surface layer of the printed circuit board. The electrical circuit includes an electrical trace that is in electrical connection with a test pad provided for accessibility on the surface layer, the test pad being sized and shaped for probing to test an aspect of the circuit, the test pad having a conductive probe surface that is structured to provide at least one vertical surface that extends from the probe surface toward the surface layer and thus providing an edge between the vertical surface and the probe surface, the probe surface having a coating of a material to protect the conductive probe surface from corrosion.

Textured test pads for printed circuit board testing

The present disclosure relates to encapsulant compositions for use with hard disk drive devices.

Encapsulant composition for use with electrical components in hard disk drives, and related electrical components and hard disk drives

Aspects of the disclosure are directed to apparatuses and methods involving an electrical connector and methods thereof. As may be consistent with one or more embodiments, an interposer includes respective barrier layers having barrier material that is coplanar with, and laterally surrounds, traces having connected via pads. Vias connect pads of stacked pairs of the traces in different ones of the barrier layers. The traces vary in width along their respective lengths. The barrier material is offset from each trace by a continuous gap having a length extending around the trace, with the gaps extending around each stacked pair being offset from one another along the majority of their respective lengths.

Interposer with offset-stacked traces

A microelectronic device includes a die having an active surface and a non-active surface. To assemble the microelectronic device, the active surface of the die is placed on a substrate. A first material is dispensed between the active surface of the die and the substrate. A second material is dispensed on at least a portion of the non-active surface of the die. The second material is different than the first material and the first material and the second material are simultaneously cured.

Edge coating a microelectronic device

Packaged surface mount (SMT) chips having matched top contacts and bottom contacts are stacked. Chip features are selected to provide the desired connectivity between chip layers with a greater ease of manufacture. In one embodiment, additional spacing and routing layers are optionally provided between layers. In another, chips are differentiated by optionally providing different conductor and/or nonvolatile cell configurations. In yet another, a minority of a substrate's contacts are configured for aligning with a dielectric region of a spacing layer or substrate to create very low capacitance signal paths between stacked chips.

Surface mount IC stacking method and device

Growing community of inventors

Apple Valley, MN, United States of America

Michael Richard Fabry