Lucent Technologies Inc.

Agere Systems Inc.

Michael Richard Betker

Shaun Patrick Whalen

John Susantha Fernando

Harry Dwyer

Jay Patrick Wilshire

Trevor Edward Little

Bryan Schlieder

Pramod Vasant Argade

Han Nguyen

Frank Lemmon

A method and apparatus are disclosed for establishing a bound on the effect of task interference in an instruction cache shared by multiple tasks. The bound established by the present invention is the maximum number of 'live' frames of a given task that are coexistent during the execution of an application. A 'live cache frame' contains a block that is accessed in the future without an intervening eviction. The eviction of blocks from a live frame by an interrupt causes a future miss that would not otherwise occur and evictions from live frames are the only evictions that cause misses that would not otherwise occur. The invention provides a more accurate estimate of the maximum additional execution time of a task that results from servicing an interrupt during its execution. Additional accuracy is obtained by exploiting knowledge of the character of an intervening task to achieve a tighter bound, when possible.

Method and apparatus for establishing a bound on the effect of task interference in a cache memory

A method and apparatus are disclosed for establishing a bound on the effect of task interference in an instruction cache shared by multiple tasks. The bound established by the present invention is the maximum number of 'live' frames of a given task that are coexistent during the execution of an application. A 'live cache frame' contains a block that is accessed in the future without an intervening eviction. The eviction of blocks from a live frame by an interrupt causes a future miss that would not otherwise occur and evictions from live frames are the only evictions that cause misses that would not otherwise occur. The invention provides a more accurate estimate of the maximum addition time of a task that results from servicing an interrupt during its execution. Additional accuracy is obtained by exploiting knowledge of the character of an intervening task to achieve a tighter bound, when possible.

Techniques are disclosed for implementing software breakpoints in a processor system having at least one processor coupled to a main memory and associated with an instruction cache. A breakpoint code is inserted at a particular location in the instruction cache of at least a given one of the processors, and a control indicator associated with the particular location is set to a first state which allows the breakpoint code to be returned to the given processor from the instruction cache in response to a first fetch request directed to a corresponding address. Subsequently, the control indicator associated with the particular location is set to a second state which directs that a second fetch request to the corresponding address be serviced from the main memory. The control indicator state is then changed again after a determination has been made, from the control indicator having been set to the second state, that the second fetch request to the corresponding address will be serviced from the main memory.

Processor system with cache-based software breakpoints

Techniques are disclosed for implementing software breakpoints in a multiprocessor system having a number of processors each coupled to a main memory. In an illustrative embodiment, each of the processors has an instruction cache associated therewith. An instruction for which a breakpoint is to be inserted is retrieved from a corresponding instruction address in the main memory, and a breakpoint code is inserted at the instruction address in main memory. After the breakpoint code is executed by a given one of the processors, the retrieved instruction is stored in the corresponding instruction cache for that processor, and a use-once indicator is set. The use-once indicator is operative via cache control logic to clear a validity indicator associated with the instruction after a single fetch of the instruction from the instruction cache, such that subsequent attempts by the given processor to access the instruction as stored in the instruction cache will cause the processor to retrieve the breakpoint code at the instruction address in main memory.

Multiprocessor system with cache-based software breakpoints

The present invention minimizes unneeded memory accesses by providing a digital processor having control circuit for terminating on-going memory accesses, and by a data transfer circuit that allow jump instructions to be detected sooner in the decode unit. The digital processor includes a decode unit, fetch unit and a memory controller. When the decode unit of the present invention processor determines that a discontinuity must occur in the instruction fetch sequence, it asserts a 'jump taken' signal to the fetch unit to indicate that any pre-fetched instruction codes are to be discarded and that fetching is to resume at a new fetch program counter (FPC) value. If the fetch unit is currently stalled because of an outstanding request to the memory controller unit, then the fetch unit asserts an 'abort' signal to the memory controller. The memory controller unit interprets the abort signal to mean that the current memory access activity is to be terminated as soon as possible, such that aborting the current operation does not corrupt the stored content of the memory element. In addition to the abort signal, the memory controller unit may assert A 'partial-done' signal that informs the fetch unit that some fraction of the current request has been completed. The size of the fractional data made available to the fetch unit will correspond to some size or alignment criteria such that the fetch unit may then be able to forward one instruction code to the decode unit. If the forwarded instruction is a 'taken' jump, then the decode unit will be able to abort the current fetch request sooner than if it had to wait for the full request to be satisfied.

Apparatus and method for aborting un-needed instruction fetches in a

A first register stores a value that can be used as a pointer to indirectly address a second register. The first register is referred to as a pointer register and the pointer as a register pointer. The second register may be a conventional register that stores a conventional register value (i.e., a data value or a pointer to a data value stored in external memory) or another pointer register. In certain embodiments, a pointer register can also be used to store conventional register values. Pointer registers of the present invention can be used to implement efficiently certain types of digital processing, such as circular buffers, vector processing, convolutional processing, and partitioned processing, using data in registers rather than memory.

Pointer register indirectly addressing a second register in the

A technique for configuring a processor allows the processor to interface with external buses of different types; for example, busses having different data widths. Configuration data is stored in a memory, typically a read-only memory, and transferred to the processor during a system configuration period. An initial configuration fetch may be accomplished to retrieve the configuration information prior to executing an actual processor instruction. Alternatively, the configuration information may be included in an actual instruction word. The system configuration period typically occurs during the initial power-on sequence, but may occur at other times.

Integrated circuit with programmable bus configuration

The invention specifies on-chip address matching hardware which is external to the processor core and prefetch queue of a microcontroller, and instruction decoding logic to mark and process breakpointed instructions. The address matching hardware includes a number of equality comparators which observe addresses on an intermodule bus of the microcontroller. This bus is not directly connected to the processor core and handles both instruction and data traffic. In one embodiment, four such matchers are provided. When an instruction address matches one of the breakpoints, a code indicating the breakpoint number is returned along with the instruction fetched. This breakpoint code is entered into the prefetch queue in the processor core, along with the instruction. When that instruction reaches the decode stage, the breakpoint information is decoded along with the instruction. The breakpoint actions associated with an instruction only occur when the instruction is about to be issued for execution. The decode logic of the processor core uses additional signals from the external matching hardware to determine if the breakpoint number associated with the current instruction is enabled to cause a breakpoint event. If the instruction is enabled to cause an event, the decode logic causes the event to happen. Regardless, the decode logic signals the external matching logic that a breakpointed instruction has been detected. When a breakpoint event is not enabled, the external matching logic can take other action such as updating a counter or starting execution monitoring activities.

Apparatus and method for decoding instructions marked with breakpoint

A digital microprocessor having a processor core is provided with trace recording hardware capable of receiving, analyzing and temporarily storing data indicative of program instructions (i.e., instruction types) executed by the processor core and of their respective addresses. The trace recording hardware outputs an abbreviated real-time program trace, containing minimum data necessary to reconstruct a full program trace, via a JTAG port to an external debug host computer where a user may reconstruct the full program trace with reference to a program listing. The abbreviation scheme used by the trace recording hardware is preferably achieved by comparing instruction types received from the processor core to at least one pre-defined instruction type, and abbreviating or discarding the corresponding address information as a function of the particular instruction type. The trace recording hardware may be set into one of two modes by the user. In the first mode, the trace recording hardware stalls the processor core when it reaches its maximum storage capacity for instruction type and/or address data until storage becomes available. In the second mode, when the trace recording hardware becomes full it discards data received from the processor core and stores an overflow indicator. The program trace may be initiated and stopped by the user or by signals internal to the digital microprocessor.

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Allentown, PA, United States of America

Michael Richard Betker