Microchip Technology Inc.

Michael Rentschler

Venkatraman Iyer

Martin Miller

Thorben Link

Dixon Chen

John Junling Zang

Venkat Iyer

Bernd Sostawa

Synchronization for audio systems and related systems and circuitry are disclosed. An audio system includes a word select line of a digital audio interface, a serial clock line of the digital audio interface, and hardware circuitry. The hardware circuitry is configured to provide a word select signal to the word select line and a serial clock signal to the serial clock line. The word select signal is configured to indicate channels of a serial data signal provided to a serial data line of the digital audio interface. The hardware circuitry is also configured to synchronize the serial clock signal to a clock reference stream of an audio stream communicated via a network interface.

Time-synchronized hardware controllers and related audio systems and circuitry

Various examples relate to a wired local area network (WLAN) including a shared transmission medium. An apparatus includes a beacon counter and an operational mode controller. The beacon counter is operably coupled to a line of a shared transmission medium of a wired local area network. The beacon counter is to count beacon signals on the line and determine a beacon count over a predetermined time period, or a beacon rate of the beacon signals. The operational mode controller is to control the apparatus to take over operation as a master node of the wired local area network based, at least in part, on a maximum bus cycle length of bus cycles on the line and responsive to the beacon count or the beacon rate.

Changing a master node in a wired local area network and related systems, methods, and devices

Various embodiments relate to a wired local area network (WLAN) including a shared transmission medium (e.g., a 10SPE network). A method may include detecting an event in a WLAN including physical level collision avoidance (PLCA). The method may also include disabling a beacon of a first node operating as a master of the WLAN in response to the event. Further, the method may include enabling a second node to operate as the master of the WLAN.

Disclosed embodiments relate, generally, to traffic shaping at a network segment having a shared bus. Some embodiments relate to performing aspects of the traffic shaping at a physical layer device. In some cases, transmit timeslot signaling may be tuned at a physical layer device to create transmit timeslots that are aligned with the traffic shaping profile.

Media access for time-sensitive and best efforts data packets, and related systems, methods and devices

Various embodiments relate to wired local area networks. A method may include detecting, at a node in a wired local area network, at least one event. A physical layer device of the network node is configured to implement a physical level collision avoidance (PLCA) sublayer. The at least one event may include at least one of an amount of data stored in a first-in-first-out (FIFO) buffer of the node being at least a threshold amount, and a received packet being a precision time protocol (PTP) packet incurring variable delay. The method may further include emulating a collision at the node in response to the at least one detected event.

Emulating collisions in wired local area networks and related systems, methods, and devices

A microcontroller includes a packet matching circuit, a hardware timer circuit, and a processor. The packet matching circuit is configured to match contents of received packets to the microcontroller and identify whether a packet has been received. The hardware timer circuit is configured to provide a synchronization timestamp based on a signal from the packet matching circuit that a synchronization packet has been matched, and provide a follow-up timestamp based on a signal from the packet matching circuit that a follow-up packet has been matched after reception of the synchronization packet. The processor is configured to adjust a clock base to determine a synchronized clock base based upon the synchronization timestamp and upon the follow-up timestamp.

Performing PHY-level hardware timestamping and time synchronization in cost-sensitive environments

A 10SPE network node includes a processor, a memory, instructions in the memory configured to cause the processor to generate data to be sent to other nodes, and a network stack. The network stack includes circuitry configured to delay transmission of data in a sending slot in a transmission cycle on a 10SPE network based upon a bandwidth sharing scheme.

Growing community of inventors

Baden-Wuerttemberg, Germany

Michael Rentschler