Infineon Technologies Ag

Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Other

Eesy-ic Gmbh

Michael Reinhold

Frank Ohnhaeuser

Andreas Wiesbauer

Juergen Roeber

Hong Chen

Mikael Badenius

Ulrich Reichold

Richard Gaggl

Miroslav Oljaca

Johann Hauer

Martin Allinger

Konstantin Schmid

Rainer Rodenheber

Jens Egerer

Frank Ohnhäuser

Frank Onhaeuser

A microphone includes a first resistor circuit for receiving a bias voltage; an offset reduction circuit coupled to the first resistor circuit; a second resistor circuit coupled to the offset reduction circuit; an amplifier coupled to the second resistor circuit configured for receiving an input signal and generating an output signal; and a capacitor circuit coupled to the amplifier, the offset reduction circuit, and the second resistor circuit.

Offset reduction for silicon microphones

A device includes a readout circuit coupled between an input node and an output node; a microelectromechanical systems (MEMS) device coupled to the input node; and a first charge controlled clamp circuit coupled between the input node and a first bias node.

Charge controlled clamp for MEMS readout circuits

Charge controlled clamp for mems readout circuits

In various embodiments, a measuring arrangement is provided. The measuring arrangement may include a micromechanical sensor including a capacitor, a bridge circuit including a plurality of capacitors, at least one capacitor of which is the capacitor of the micromechanical sensor, an amplifier coupled, on the input side, to an output of the bridge circuit, a DC voltage source configured to provide an electrical DC voltage, a chopper including at least one first charge store and a switch structure, The switch structure is configured to couple the first charge store alternately to the DC voltage and the bridge circuit for the purpose of coupling an electrical mixed voltage into the bridge circuit.

Circuit architecture for a measuring arrangement, a level converter circuit, a charge pump stage and a charge pump, and method for operating same

In various embodiments, a level shifter circuit is provided. The level shifter circuit may include a signal source and a level shifter. The signal source, on the output side, is capacitively coupled to an input of the level shifter. The signal source and the level shifter are galvanically isolated from one another.

Circuit architecture for a measuring arrangement, a level shifter circuit, a charge pump stage and a charge pump, and method for operating same

The device comprises a successive approximation register, a capacitive digital-to-analog converter comprising a plurality of capacitors, the plurality of capacitors being coupled with a first side to a common node; a comparator coupled to the common node and being adapted to make bit decisions by comparing a voltage at the common node with another voltage level, and a SAR control stage for providing a digital code representing a conversion result. The device is configured to operate in a calibration mode, where the device is configured to sample a reference voltage on a first capacitor of the plurality of capacitors by coupling one side of the first capacitor to the reference voltage, to perform a regular conversion cycle with at least those capacitors of the plurality of capacitors having lower significance than the first capacitor and to provide the conversion result of the regular conversion cycle for calibrating the first capacitor.

Electronic device and method for measuring differential non-linearity (DNL) of an SAR ADC

The modulator comprises a first and second integration stages, and a comparator, the first integration stage is fully differential having: an amplifier, sets of input sampling capacitors and feedback capacitors, and the first integration stage is configured to sample the analog input voltage on a set of input capacitors during a first portion of a clock cycle and on a set of input capacitors during a second portion of the clock cycle and to sample the feedback reference voltage on a set of feedback capacitors during the first portion of the clock cycle and on a set of feedback capacitors during the second portion of the clock cycle, and the first set of feedback capacitors and the second set of feedback capacitors are randomly selected out of the plurality of sets of feedback capacitors from cycle to cycle.

Electronic device and method for analog to digital conversion according to delta-sigma modulation using double sampling

Successive approximation register (SAR) analog-to-digital converters (ADCs) generally employ capacitive digital-to-analog converters (CDACs) to perform data conversions. In these CDACs, matching of capacitive values is important, and for conventional high resolution SAR ADCs, complex trimming or calibration procedures can be too costly. Here, however, a SAR ADC is provided that performs error correction so as to reduce the overall cost compared to conventional SAR ADCs.

Digital trimming of SAR ADCs

An apparatus for analog-to-digital conversion using successive approximation is provided. There is a successive approximation register or SAR controller for providing a digital code representing a conversion result, and an integral non-linearity (INL) compensator configured to provide an INL compensation signal for reducing INL of the analog-to-digital conversion in response to the digital code.

SAR ADC and method with INL compensation

A resolver arrangement that is inexpensive and yet offers high resolution and high noise rejection includes a carrier signal generator and two processing channels each of which has an analog input connected a different one of the stator coils and a channel output. Each of the processing channels includes a sigma-delta modulator with an output that supplies a bit-stream representative of an analog input signal received from a respective stator coil. Each channel also includes a first digital filter that receives the bit-stream from the sigma-delta modulator and converts the bit-stream to intermediate digital data-words. In addition, each channel has a digital synchronous demodulator that demodulates the intermediate digital data-words in synchronism with the carrier signal providing demodulated data-words. Finally, each channel has a second digital filter that averages the demodulated data-words and supplies digital output data-words on the channel output, the carrier signal being suppressed in the output data-words.

Resolver arrangement

An integrated circuit for use with an external Hall sensor that permits to at least substantially cancel out the temperature drifts of the Hall sensor, as caused by the temperature drift of the current supplied to the Hall sensor, and the gain of the Sigma-Delta modulator. Specifically, the circuit provides an integrated circuit for use with an external Hall sensor, that has an analog input for application of a Hall voltage from the Hall sensor, a digital data output and a current output for connection to a current input of the Hall sensor. The integrated circuit comprises a Sigma-Delta modulator with an input connected to the analog input and an output connected to the digital data output. An internal reference voltage source is also included in the integrated circuit, and an internal current source is connected to the current output for the Hall sensor. The internal reference voltage source is used as a reference in the current source that determines the amount of current supplied to the Hall sensor, and is also used in the Sigma-Delta modulator as a reference that determines the input voltage range. Since the same reference voltage source is used by the current source for the Hall sensor and by the Sigma-Delta modulator, the temperature drifts of the Hall voltage and the gain of the Sigma-Delta modulator cancel each other. Other benefits are low noise and an excellent common mode rejection.

Integrated circuit for use with an external hall sensor, and hall sensor module

A multi-mode interface circuit for coupling a delta sigma modulator ( ) to a processor includes a decoder for decoding mode selection inputs to produce a plurality of control signals controlling an oscillator and a plurality of multiplexers. The oscillator is enabled to produce a first clock signal (INTCLK). The first clock signal or an external clock signal (EXTCLK) is multiplexed as a second clock signal ( ) to the input of a code generator circuit ( ), causing it to generate a clock input signal (MCLK) applied the delta sigma modulator, third and fourth clock signals ( ), and a phase-shift-modulated signal ( ) in response to both the second clock signal and a 1-bit data signal (MDAT) produced by the delta sigma modulator. One of the third and fourth clock signals and a ground signal is multiplexed to a clock conductor ( ). The phase-shift-modulated signal or the 1-bit data signal is multiplexed onto a data output conductor ( ).

Flexible interface circuit and method for delta sigma A/D converters

A method for setting the trigger power of transmitter diodes that transmit data via optical paths allows the transmission power to be adjusted and adapted to the communication distance. The trigger power is determined for the present communication distance on the basis of a test signal before data transmission begins. A circuit arrangement implementing the method includes a driver circuit with a switching device that switches a circuit junction point selectively to a supply voltage or to a constant reference voltage, a voltage-controlled resistor which delivers the driver current and is controlled from the circuit junction point, and a voltage-controlled measuring resistor which delivers a measured current with a fixed relationship to the driver current and is controlled from the circuit junction point. Since the set trigger power can be reduced, the power consumption for data transmission can be reduced considerably.

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Erlangen, Germany

Michael Reinhold