Analog Devices,inc.

Other

Analog Devices Technology

Analog Devices Global Unlimited Company

Michael Ray Elliott

Frank M Murden

Brad Porcher Jeffries

Joseph Michael Hensley

Franklin Marshall Murden, Ii

Carl W Moreland

Scott Gregory Bardsley

Ravi Kishore Kummaraguntla

Johan H Mansson

William Thomas Boles

Ahmed Mohamed Abdelatty Ali

Carroll Clifton Speir

James C Camp

Bryan Scott Puckett

John Kevin Behel

Robert Schell

Michael D Keane

Marvin J Young

Harvey J Ray

Axel Zafra-Petersson

Axel Zafra Petersson

William T Boles

This invention provides an ornate method and design to create a PSP panel assembly mosaic for radiography operations. There is no similar design or method as taught herein. Having an integrated attachment point allows a superior foundation to secure PSP panel assemblies together with unique brackets allowing for modular attachments, improving performance, and capabilities. All current options utilize external methods that are not dependable, bulky, and are not modular. The main benefits of this method are a more secure connection, better image quality, fewer backscatter deposits, lightweight, ease of use, and smaller boxes needed to carry components.

PSP mosaic builder

Disclosed herein are differential amplifiers for improved slew performance. In some embodiments, a differential amplifier may receive positive and negative input signals at first and second transistor branches, respectively; provide a dynamic bias current to the first and second transistor branches, responsive to the positive and negative input signals; and provide positive and negative output signals at the second and first transistor branches, respectively.

Differential amplifiers with improved slew performance

In one aspect, a current source is provided to limit noise and offset. In one embodiment, a source transistor is provided, with current sourced at the drain. A feedback network runs from the source node to the gate. The feedback network produces voltage gain by a transconductance, such as a transistor. Appropriate capacitors are also provided, and two pairs of switches are disposed to provide offset cancellation by toggling between gain and clamp modes in the switched capacitor architecture.

Low-noise current source

A transmission system may include an oscillator, a serializer, and a driver. The oscillator may generate at least two clock signals. The serializer may modulate a plurality of data streams based upon the at least two clock signals and a plurality of channels of data. The driver may receive and combine the plurality of data streams into a single output data stream, wherein the single output data stream has a clock frequency higher than frequency of each of the at least two clock signals.

System and method of clock generation in high speed serial communication

A system and method are described herein that provide for the calibration of the offset of a comparator on a per-comparator basis. An injection is made to the comparator at determined injection points using a low-power DAC, to calibrate the offset of the comparator. The DAC can be selectively controlled by a digital codeword that is generated based on an output of the comparator and the comparator's offset. Further embodiments of the invention present a system and method for calibrating the offset of a comparator of a flash ADC in each stage of a pipeline ADC. The system and method may provide for the calibration in a manner without affecting the speed of the pipeline ADC or adding significant power to the pipeline ADC.

Use of logic circuit embedded into comparator for foreground offset cancellation

A multiplying analog-to-digital converter ('MDAC') that reduces the power consumption of the MDAC by at least 2.3 times by improving the feedback factor. The amplifier may include a feed forward approach in which the input capacitor (also referred to as 'sampling capacitor') is buffered by a common gate amplifier to improve bandwidth by removing input and parasitic capacitance terms from the global feedback loss. THe amplifier may also use an alternate form of local compensation, for example, cascode compensation. The amplifier may also further include an alternate way to reduce parasitic capacitance with a buffer.

System and method for improving speed and power in a switched-capacitor amplifier

A system provides for a serial transmitter with multiplexing and driving functionality that is combined into a single stage to increase the overall speed of the serial transmitter. The single stage includes a dynamic impedance that is configured in parallel with a multiplexing driver to reduce the input capacitance and set the correct output impedance. The single stage can be implemented as a stacked or cross-coupled XOR logic circuit or a stacked or cross-coupled multiplexer ('mux') as the multiplexing driver. In an embodiment where a mux is used as the multiplexing driver, a clock can be injected into the mux driver to overcome inter-symbol interference.

Architecture for high speed serial transmitter

A charge pump circuit can include a first pair of transistors having connected sources and gates configured to receive a first pump signal and an inverse first pump signal and a second pair of transistors having connected drains and gates configured to receive a second pump signal and an inverse second pump signal, sources of the second pair of transistors being connected to drains of the first pair of transistors at first and second connection nodes, wherein the first and second pair of transistors are all of the same transistor type and provide an output current in response to the first and second pump signals. The charge pump circuit can also include a voltage stabilizer circuit connected to the second connection node and configured to regulate the second connection node to have a voltage within a predetermined range about a selectable voltage. Duty cycle stabilizers and control loops such as delay locked loops can include the charge pump circuit.

Low-offset charge pump, duty cycle stabilizer, and delay locked loop

Data transmitter embodiments are provided which are particularly useful as interface devices for accurate and reliable transmittal of data from high-speed data system devices such as analog-to-digital converters. Transmitter embodiments have been found to provide excellent fidelity of data transfer at high data rates (e.g., 4 gigabits/second) while consuming only a portion of the power of many conventional transmitters and requiring only a portion of the layout area of these transmitters. Transmitter embodiments provide effective control of transmitter parameters such as matched impedances, data symmetry, common-mode level, data eye and current drain.

High-speed data transmitters

A system and method for playing a poker game. The system is implemented either through a software application or through a physical game environment. The system integrates a card elimination table which has a range of attack elements and range of removable elements. The attack elements are correlated to the removable elements so that when an attack card element is played, the removable elements correlated to that particular attack card element are eliminated from the game.

Poker game

Operational amplifier embodiments are provided to enhance amplifier parameters such as bandwidth, stability, and headroom. In an amplifier embodiment, transistor followers are arranged with first and second differential pairs to facilitate selective positioning of first and second transfer function poles to enhance bandwidth and resistors and inductors are arranged to facilitate selective positioning of complex third transfer function poles to enhance phase margin. In another amplifier embodiment, the transistor followers are arranged to reduce headroom limitations to thereby enhance the voltage swing of output signals.

Operational amplifiers with enhanced parameters

Clock processors are provided to economically control system and data clocks in high-speed signal converters. The processors generally include at least one of a delay-locked loop, phase-locked loop or a duty cycle stabilizer which generates an error signal in its operation. In the example of a stabilizer, it is configured to respond to an input clock to initiate a first portion of each cycle of the system clock and to include a control loop to provide an error signal that controls a second portion of the cycle to thereby maintain a selected duty cycle. The processors also include a data clock aligner configured to share the error signal and provide a data clock that is delayed by a selected delay from a selected one of the input and system clocks. In addition to providing effective control that is independent of disturbing effects (e.g., temperature and clock rate), the shared use reduces processor costs.

Clock processors in high-speed signal converter systems with data clock aligner sharing error signal produced in duty cycle stabilizer

A jousting element for use in a game. The jousting element has a body which is arranged around a cylindrically aligned vertical axis. The body is configured to rotate about the vertical axis and to be carried above a playing surface. A traveling component connected to the body enables the body of the jousting element to be carried above the playing surface along multiple directions of travel. Attached to the body is a first playing component. The first playing component enables the jousting element to engage a second jousting element.

Jousting toy

Signal converter system embodiments are provided to substantially reduce symmetrical and asymmetrical conversion errors. Signal-processing stages of these embodiments may include a signal sampler in addition to successively-arranged signal converters. In system embodiments, injected analog dither signals are initiated in response to a random digital code. They combine with a system's analog input signal and the combined signal is processed down randomly-selected signal-processing paths of the converter system to thereby realize significant improvements in system linearity. Because these linearity improvements are realized by simultaneous processing of the input signal and the injected dither signal, a combined digital code is realized at the system's output. A first portion of this combined digital code corresponds to the analog input signal and a second portion corresponds to the injected analog dither signal. The final system digital code is realized by subtracting out the second portion with a back-end decoder that responds to the random digital code.

Pipelined converter systems with enhanced linearity

Embodiments of the present invention provide a pipeline ADC front-end sampling structure that provides a continuous time input signal to a flash comparator for sampling. By providing a continuous time input signal to the flash comparator, no delay is introduced from the need to transfer a DC charge representing the sampled input to the flash comparator. Matching sampling networks in the residual generator and the flash comparator are avoided due to the high bandwidth response requirements of the residual generator and the flash comparator when operating on high frequency input signals.

Growing community of inventors

Summerfield, NC, United States of America

Michael Ray Elliott